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date change list D D 0 HAIER V.0 Date: Thursday, December 0, 0 Sheet of MSDA00HTA A Revision History.0

VDD ORE POWER.V ST POWER U TI ORE POWER +V_NORMAL L.uH SW V POWER ONNETOR R 0K EN N Power_Main +V_NORMAL VREG R 0 0.uF ST 0uF/.V 0.uF 0uF/.V 0uF/.V U +V_Standby SS R 0 D D P-ADJUST 0uF/V 0uF/V 0.uF 0.uF uf 0P AMS-. 0 0 V_VSENSE PW-ON/OFF-INV P-ON/OFF 00K 0.0uF R.0K/% R /0R Standby:L F R /K R /K +.V_Normal +.V_Standby R R 0K +V_Standby Normal: H R 0K K/% R0 Q D D Q /.K 0.uF 0.uF.uF VD0 VDI R VDD R0.K R /.K VID VID0 G S S G VID PW-ON/OFF-INV R0 /K R0.K N00 /N00 +V_Standby +.V_Standby R 0 R.K.0V L.K Q R 00R PWR-ON/OFF PWR-ON/OFF /0 H.K.V IN OUT ADJ!!! A D/D +V_US.V POWER R.K P-ON/OFF R 00 R 0 R Q K VL_TRL VL_TRL U 0.uF 0K 0 +V_NORMAL +V_US +V_Normal U R TI L.uH AMS-ADJ +V_US V SW R 0K 0R R EN RT_NTL_IN RT_NTL_IN R /0.K VREG 0.uF +.V_Normal +V_Normal P-ADJUST ST R /0 R K RT_NTL_OUT 0P R R0 SS 0.uF R Q.K R R 00K/%/K 0uF/.V 0uF/.V RI_ADJ 0 0.uF 0.uF.uF 0K 0R /.uf 0uF/V 0uF/V 0.uF uf 0.0uF /0.uF 00K F R0 K/%/.K MAIN V IN OUT ADJ.V POWER LVDS POWER U +V_NORMAL +V_US L /F/A V-Panel L Q AMS-. F/A +V_Standby +V_Normal +.V_DDR U R AO0A R.K +.V_Normal 00K 0uF/V R 0R ADJ 0.uF 0.uF 0.uF R /0R EN OUT IN OUT R 0 +V_Normal R IN OUT 0.uF/0V 0uF/0V 0.uF 0uF/0V 00K uf/0v 0uF/0V 0.uF AP R R 0.uF.uF 0.uF 0R Q K/% DDR POWER IN OUT ADJ R 0K/% PANEL_ON/OFF 0 R.K R.K H H H H MSDA00HTA System power.0 ustom Thursday, December 0, 0 Date: Sheet of H H0 H H H PAD H PAD H PAD H PAD

video NAND & I & TS & Front End VDDLV K U00 AVDDLV T H J VDD T PMIA VDD R V W VDD K PMDATA0 TSDATA0 VDD A T R H PMDATA TSDATA VDD W P H V_VSENSE VDD VDD F Y PMDATA TSDATA R H PMDATA TSDATA VDD F0 V TS Y J PMDATA TSDATA VDD_PU H0 W V K J J0 U PMDATA TSDATA W VDD_PU PMDATA (In/Out) TSDATA VDD_PU lose to MST I K0 U T J PMDATA TSDATA VDD_PU L0 R with wide trace PM_A[:0] PM_A0 TSLK N0 T DVDD_DDR G0 U00E PM_A PMADR0/NF_D0 TSVALID T DVDD_DDR R R R RIN0 RIN0 PM_A G nf 0 PMADR/NF_D TSSY U K VGA-Rin ETHERNET U G GIN0N GIN0N MDI_TN PM_A H R R0 nf 0 RIN0P VSENSE K nf 0 GIN0 GIN0 GIN0M TN A PMADR/NF_D R MDI_TP MDI_TN PM_A J R R0 PMADR/NF_D J T T0 VGA-Gin AVDDP T R R IN0 IN0 MDI_RP MDI_TP PM_A AVDDP K nf 0 GIN0P TP PMADR/NF_D TS0DATA0 J VGA-in VGA R U0 T IN0P RP MDI_RN MDI_RP PM_A AVDD_MOD L VGA_HSY VGA_HSY RN A PMADR/NF_D TS0DATA Y V MDI_RN PM_A PMADR/NF_D TS0DATA N H T R0 VGA_HSY AVDD_DMPLL T VGA_VSY VGA_VSY HSY0 PMADR/NF_D TS0DATA AVDD_DMPLL F VGA_VSY J V0 W0 VSY0 PMADR TS0 TS0DATA H V T AVDD_NODIE U D R R RIN AVDD_NODIE J nf PMADR TS0DATA Y U YPbPr_PR D R R nf GINN RIN System-RST (In) Y0 PMADR0 TS0DATA AVDDP lose to MST I K M H V P0 AVDD_NODIE U GIN GINN AVDD_AU L R R nf 0 M RINP HWRESET YPbPr_Y MIS Y PMADR TS0DATA R GIN GINM XTALI VDD U R R IN IN YPbPr XIN W PMADR TS0LK L U GINP XTALO PMADR TS0VALID P VDDP_PLL J nf L Y W YPbPr_P nf SOGIN SOGIN INP XOUT PMADR TS0SY V0 K 0R R L SOGIN IR-in N AVDD_MIU0 G IRIN F W0 PMIRQA_N _D A W G 0.uF _D F P 0.uF PMOE_N W G RINP PMIORD_N _ N N US W US0_D- P N GINM US0_D+ US0_D- DVDD_NODIE E M GINP US0_DM A V PME_N SART V PMWE_N uf US0_D+ DVDD_NODIE A J INP US0_DP P PMD_N SOGIN0 US_D- VIFP L F P HSY US_DM W R PM_RESET T 0.uF US_D+ US_D- 0.uF _EFUSE US_D+ VIFM L A P Y Y PMREG_N IP VSY US_DP IM T L TEST W PMIOWR_N US_D- VSENSE_ F US_D- VOM0 VOM0 US_D+ W R US_DM W PMWAIT_N R R nf VOM VS V US_DP US_D+ EMM_MD EMM_LK Y V VS0 VS0 EMM_MD EMM_RSTZ EMM_MD W AV-VIDEO R R nf 0 U T EMM_LK VS EMM_RSTZ EMM_LK EMM_RSTZ V U VS0 EMM IN U EMM_MD R R VS VS EMM_LK FRONT-END V nf EMM_RSTN AV-VIDEO R 0K Y V_TU VS_OUT VS_OUT NAND_ALE VS_OUT R IF_AG V VSOUT OUT W NAND_ALE NAND_WPZ V NF_ALE/EMM_D R0 0R NAND_WPZ IF_AG_T MSDA00HTA NAND_EZ NF_WPZ/EMM_D V T NAND_EZ NAND-EZ NF_EZ/EMM_D TGPIO0 Y NAND-EZ NAND/EMM P NAND_LE NF_EZ/EMM_D TEST() W W nf NAND_LE MSDA00HTA NAND_REZ NF_LE/EMM_D I_SKM Y V NAND_REZ NAND_WEZ NF_REZ/EMM_D I_SDAM W NAND_WEZ losed to MSTI NAND_RZ NF_WEZ/EMM_D V NAND_RZ NF_RZ/EMM_D0 Place & 0 on V_TU DVDD_DDR VDDLV J R.K VDD bottom side for debug MSDA00HTA R.K L0 +.V_VDD 00 0 T_SL F 0 /pf /pf T_SDA SHIELD 0 uf NAND FLASH I 0.uF.uF.uF 0.uF 0.uF 0.uF /0.uF U00F HDMI & Audio GPIO & LVDS 0uF 0.uF 0.uF uf 0.uF 0 0 HDMI-RX0P HDMI-RX0N HDMI-RXP HDMI-RXN HDMI-RXP HDMI-RXN HDMI-LKN HDMI-LKP HDMI-SL HDMI-SDA HDMI-HPDIN HDMI-AR HDMI-E HDMI-RX0P HDMI-RX0N HDMI-RXP HDMI-RXN HDMI-RXP HDMI-RXN HDMI-LKN HDMI-LKP HDMI-SL HDMI-SDA HDMI-HPDIN HDMI-AR HDMI-E HDMI-RX0N HDMI-RX0P HDMI-RXN HDMI-RXP HDMI-RXN HDMI-RXP HDMI-LKN HDMI-LKP HDMI-SL HDMI-SDA HDMI-HPDIN HDMI-E HDMI-AR F G G H H H F F D F D D E E E D G G U00 HDMI RXA0N RXA0P RXAN RXAP RXAN RXAP RXAKN RXAKP DDDA_K DDDA_DA HOTPLUGA RXD0N RXD0P RXDN RXDP RXDN RXDP RXDKN RXDKP DDDD_K DDDD_DA HOTPLUGD E AR0 MSDA00HTA AUDIO ANALOG AUDIO DIGITAL AUL0 AUR0 AUL AUR AUL AUR AUL AUR P EARPHONE_OUTL EARPHONE_OUTR P AUOUTL AUOUTR M M L L M N M N N N R AUVRM P AUVAG R TEST() IS_IN_SD(D_FLAG) TEST() J IS_OUT_K L IS_OUT_MK J IS_OUT_WS IS_OUT_SD K SPDIF_OUT TEST() K K J G LINE_IN_L LINE_IN_R LINE_IN_L LINE_IN_R EARPHONE_OUTL EARPHONE_OUTR AUVAG AUVRM IS_IN_SD D_FLAG IS-OUT_K IS-OUT_MK IS-OUT_WS IS-OUT_SD SPDIF_OUT SPDIF_IN.uF.uF.uF 0.uF 0 pf lose to MSTAR I HD_Lin HD_Rin AV-Lin AV-Rin HD_Lin HD_Rin AV-Lin AV-Rin IS_SLK IS_MLK IS_LRLK IS_SD0 Audio Line Out L0.uH EARPHONE_OUTL L0.uH EARPHONE_OUTR AUVRM AUVAG mstar I R 00R R 00R 0uF.uF EARPHONE-OUTL EARPHONE-OUTR,,,, RI_ADJ SAR.V!!!!! VID0 VID VL_TRL M_SL M_SDA PANEL_ON/OFF PWR-ON/OFF FG-PWM0 FG-PWM RI_ADJ PWM_PM KEY0-in KEY-in VID0 SPI_SK SPI_SDI SPI_SDO SPI_SN UART-RX UART-TX D_LR_in VID LED_R VL_TRL M_SL M_SDA PANEL_S PANEL_S ODY PANEL_ON/OFF PWR-ON/OFF R 00R R 00R UART_RX R 00R UART_TX PM_TX PM_RX R 00R R 00R R 00R LVA0P LVA0N LVAP LVAN LVAP LVAN LVALKP LVALKN LVAP LVAN LVAP LVAN LV0P LV0N LVP LVN LVP LVN LVLKP LVLKN LVP LVN LVP LVN AMP-MUTE LED_ RST_AMP LVA0P LVA0N LVAP LVAN LVAP LVAN LVALKP LVALKN LVAP LVAN LVAP LVAN LV0P LV0N LVP LVN LVP LVN LVLKP LVLKN LVP LVN LVP LVN AMP-MUTE TP +.V_Normal Place 0 & 0 on bottom side for debug AVDDP +.V_Standby V.VA +.V_Standby AVDD_NODIE 0.uF +.V_Normal 0uF L0 F L0 F VDD Place 00 & 0 on bottom side for debug 0.uF 0.uF L0 F L0 F L0 F /0.uF AVDD_DMPLL Place, on 0 bottom side for debug /0.uF Place 0 on bottom side for debug Place & 0 on bottom side for debug /0.uF MSDA00HTA lose to MSTAR I with width trace 0uF 0.uF /0.uF /0.uF Mode Selection config +V_Standby +.V_Standby +.V_Normal SPI_SDI MUTE be pull up.vstb R00.K R0 SPI_SDI R R.K PWM_PM R /.K R /.K IS-OUT_WS R /.K R.K IS-OUT_K R.K R0 /.K IS-OUT_MK R R.K FG-PWM R R.K FG-PWM0 RESET // HIP_ONFIG {IS_OUT_K, IS_OUT_MK, PWM, PWM0} _NO_EJ (External SPI) _W/O_Scramble (Internal SPI/OTP) _W/_Scramble (Internal SPI/OTP) A_EMM_NO_EJ A_SPI_NO_EJ (External SPI) A_SPI_EJ (External SPI) A_ROM_NO_EJ A_EMM_M_EJ A_ROM_EJ A_WOS (Internal SPI/OTP) A_WS (Internal SPI/OTP) SUS A_EMM_M_NO_EJ A_EMM_M_EJ DUS // {PM_PWM} oot from EXT_FLASH 'b0 oot from INT_FLASH 'b //{PAD_PM_SPI_DI} NODIE_STALE 'b0 DIE_STALE 'b rystal 'b0000 (0x0) 'b000 (0x) 'b000 (0x) 'b00 (0x) 'b000 (0x) 'b00 (0x) 'b00 (0x) 'b0 (0x) 'b000 (0x) 'b00 (0x) 'b00 (0xa) 'b0 (0xb) 'b00 (0xc) 'b0 (0xd) 'b (0xf) onnector +.V_Normal R R R0 R +.V_Standby KEY KEY0 M_SL M_SDA +V_Standby R.K IR R 00 LED-R LED- nf nf IR-in pf LED-R R 0K +.V_Standby +V_Normal +.V_Standby +V_Normal +.V_Normal +.V_Normal R R N.K.K R D_SY_Glass.K R KEY0 R K KEY0-in R K ODY /.K KEY R K KEY-in R /k D_SY_Glass PWM_PM R /.K Q /0 0.uF 0.uF D_ON R 0K LED_R +.V_Normal R R /0R /0R LED- R /0K /Q R /0K LED_ 0 D_SY_Glass R 0R/ D_SY_OUT DEUG UART_TX UART-TX UART_RX UART-RX +V_Standby MUST pull high to VST R0 R0 ISP AND VGA EDID FLASH UART_TX UART_RX PANEL_S D_FLAG D_LR_in PANEL_S RST_AMP VL_TRL M_SL M_SDA PANEL_S D_FLAG D_SY_OUT PANEL_S RST_AMP +.V_Standby +.V_Normal R XTALO 0R pf +.V_Standby R0 D00 00K AV ==*L- R 0K R U0 M SPI_SN Y00 VDD E# SPI_SDO.000MHz SPI_SK SO #F_WP.uF HOLD# R0 XTALI pf SPI_SDI SK WP# 0K Q00 SI 0 NOTE: 0PPM MXL0 R 0.uF K System-RST.uF 0.uF MSDA00HTA Size Document Number MSDA00 Rev.0 ustom Thursday, December 0, 0 Date: Sheet of R.R/% R R R R R R.uF N PH-A R.K R0.K R.R/% TP TP 0.uF L00 M M M H D D G A A H E H G G E J H U R R F F K M PWM0 PWM PWM PWM_PM U00D SAR0 SAR SAR TEST() PWM SAR PM_SPI_SK PM_SPI_SDI SPI PM_SPI_SDO PM_SPI_SZ/GPIO_PM[] DDA_K/UART0_RX DDA_DA/UART0_TX UART UART_RX UART_TX PM_UART_TX/GPIO_PM[] PM_UART_RX/GPIO_PM[] I_SKM/I_DDR_K I_SDAMI_DDR_DA GPIO GPIO GPIO GPIO_PM[0] GPIO_PM[] TEST() TEST() NORMAL GPIO PM GPIO LVDS L/Dimming P LVA0P LVA0M N R LVAP LVAM P R0 LVAP LVAM R T0 LVAKP LVAKM T U LVAP LVAM T V LVAP LVAM U J0 LV0P LV0M J K0 LVP LVM K L LVP LVM K M LVKP LVKM L M0 LVP LVM M N0 LVP LVM N SPI_K SPI_DI SPI_K SPI_DI VSY_LIKE N N P N P L0 F /0.uF /0.uF N IR_LED J0 ON-.0.K.K R.K F N Key R 00K nf R.R/% R.R/% +.V_DDR AVDD_MIU0 +.V_DDR 0 0.uF 0uF 0.uF

MSD MIU MIU0 connect MIU0 U00A A_DDR_MLK R 0R A-DDR_MLK MIU0 E A_DDR_A0 A_DDR_MLKZ R 0R A-DDR_MLKZ A_DDR_A0 D0 A_DDR_A A_DDR_A D A_DDR_A A_DDR_A A0 A_DDR_A A_DDR_RASZ A-DDR-RASZ_ A_DDR_A D A_DDR_A A_DDR_ODT A-DDR-ODT_ A_DDR_A _DDR_A U0 A_DDR_A D A_DDR_A A_DDR_ASZ A-DDR-ASZ_ A_DDR_A A_DDR_A RP0 RX A_DDR_A E A_DDR_A A_DDR_A0 A-DDR-A0_ A_DDR_A D A_DDR_A A_DDR_A D D A_DDR_A0 A_DDR_A A-DDR-A_ A-DDR-A0_ K A_DDR_DQSL A_DDR_A0 A_DDR_A A_DDR_A A-DDR-A_ A-DDR-A_ A0 DQS E0 L D A_DDR_DQSL A_DDR_A E A_DDR_A RP0 RX A-DDR-A_ A DQS# L A_DDR DDR_A A-DDR-A_ A K A_DDR_DML A_DDR DDR_A A_DDR_A A-DDR-A_ A-DDR-A_ A DM/TDQS D L A A_DDR_A A_DDR_DQL0 A_DDR_RESET A-DDR-RESET_ A-DDR-A_ A NU/TDQS# L A_DDR_DQL0 A_DDR_DQL A_DDR_A A-DDR-A_ A-DDR-A_ A M A_DDR_DQL A_DDR_DQL A_DDR_DQL A_DDR_A A-DDR-A_ A-DDR-A_ A DQ0 0 M A_DDR_DQL A_DDR_DQL A_DDR_DQL RP0 RX A-DDR-A_ A DQ N A_DDR_DQL A_DDR_DQL A_DDR_DQL A-DDR-A_ A DQ D M A_DDR_DQL A_DDR_DQL A_DDR_DQL A-DDR-A0_ A DQ H E A_DDR_DQL0 A_DDR_DQL A_DDR_DQL A_DDR_A A-DDR-A_ A-DDR-A_ A0 DQ D0 M D A_DDR_DQL A_DDR_DQL A_DDR_DQL A_DDR_A A-DDR-A_ A-DDR-A_ A DQ K E A_DDR_DQL A_DDR_DQL A_DDR_DQU0 A_DDR_A0 A-DDR-A0_ A-DDR-A_ A D HTQGDFR-P DQ N E A_DDR_DQL A_DDR_DQU0 E A_DDR_DQU A_DDR_WEZ A-DDR-WEZ_ A-DDR-A_ A DQ N A_DDR_DQU E A_DDR_DQU RP0 RX A J I-P-FGA-DDR J A-DDR-A0_ A_DDR_DQU E A_DDR_DQU A A0 K A-DDR-A_ A_DDR_DQU D A_DDR_DQU MVREFA_A_ A J J A-DDR-A_ A_DDR_DQU D A_DDR_DQU A_DDR_A R R A-DDR-A_ VREFA A A_DDR_DQU E A_DDR_DQU A_DDR_A R R A-DDR-A_ A A_DDR_DQU E A_DDR_DQU F F A-DDR_MLK A_DDR_DQU A_DDR_ASZ K F G A-DDR_MLKZ A_DDR_ASZ A_DDR_RASZ K# H A_DDR_RASZ E A_DDR_WEZ H MVREFDQ_A_ A_DDR_WEZ A_DDR_DML A_DDR_A A-DDR-A_ VREFDQ E A_DDR_DQML A_DDR_DMU A_DDR_A A-DDR-A_ A-DDR-KE_ A_DDR_DQMU E H G _DDR_ODT A_DDR_A A-DDR-A_ A-DDR-RASZ_ /S KE F A_DDR_ODT A_DDR_A0 A_DDR_A A-DDR-A_ A-DDR-ASZ_ /RAS G N A-DDR-RESET_ A_DDR_A0 E A_DDR_A RP0 RX A-DDR-WEZ_ /AS RESET# H A_DDR_A 0 A_DDR_A A-DDR-ODT_ /WE G A-DDR_MLK A_DDR_A D A_DDR_RESET ODT A-DDR_MLKZ A_RESET D A_DDR_KE A_DDR_MKE A_DDR_MLK A_DDR_A A-DDR-A_ A_DDR_MLK _DDR_MLKZ A_DDR_A A-DDR-A_ A_DDR_MLKZ A_DDR_DQSL A_DDR_A0 A-DDR-A0_ R A_DDR_DQSL _DDR_DQSL A_DDR_KE A-DDR-KE_ lose to DRAM 0R_% A_DDR_DQSL A_DDR_DQSU A_DDR_DQSU A RP0 RX A_DDR_DQSU A_DDR_DQSU VDDQ VDDQ VDDQ E VDDQ E VDD M VDD M VDD K VDD D VDD G VDD G VDD K VDD A VDD A R R R R ZQ Q Q Q Q Q H A A D F F J J L L N N D D 0nF MSDA00HTA MIU MIU0 power STR A_DDR_KE +.V_DDR R K R K R K R0 K/% R0 K/% VDD G VDD G VDD K VDD K VDD M VDD M VDDQ VDDQ VDDQ E VDDQ E VDD D VDD A VDD A U0 lose to DDR POWER PIN MVREFA_A_ MVREFA_A_ A-DDR-RESET_ A-DDR-RESET_ 0.uF 0.uF 0.uF 0.uF 0.uF R0 0 R0 0 0 A-DDR-A0_ A_DDR_DQSU STR K K/% 0.uF nf K/% 0.uF nf A-DDR-A_ A0 DQS L D A_DDR_DQSU A-DDR-A_ A DQS# L A-DDR-A_ A K A_DDR_DMU A-DDR-A_ A DM/TDQS MIU connect L A A-DDR-A_ A NU/TDQS# L A-DDR-A_ A M A_DDR_DQU A-DDR_MLK A-DDR_MLK_ A-DDR-A_ A DQ0 M A_DDR_DQU A-DDR_MLKZ A-DDR_MLKZ_ A-DDR-A_ A DQ N A_DDR_DQU A-DDR-A_ A DQ M A_DDR_DQU A_DDR_RASZ A-DDR-RASZ_ A-DDR-A0_ A DQ H E A_DDR_DQU 0 0 0 0 0 A_DDR_ODT A-DDR-ODT_ A-DDR-A_ A0 DQ M D A_DDR_DQU 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF A-DDR-A_ A DQ K E A_DDR_DQU0 A_DDR_ASZ A-DDR-ASZ_ A-DDR-A_ A HTQGDFR-P DQ N E A_DDR_DQU RX RP A-DDR-A_ A DQ N A_DDR_A0 A-DDR-A0_ A J I-P-FGA-DDR J A-DDR-A0_ A A0 K A-DDR-A_ A_DDR_A A-DDR-A_ MVREFA_A_ A J J A-DDR-A_ A_DDR_A A-DDR-A_ VREFA A RX RP0 A A_DDR_A A-DDR-A_ F F A-DDR_MLK_ MVREFDQ_A_ A_DDR_RESET A-DDR-RESET_ K F G A-DDR_MLKZ_ MVREFDQ_A_ A_DDR_A A-DDR-A_ K# H R A_DDR_A A-DDR-A_ H MVREFDQ_A_ K/% R0 RX RP0 VREFDQ E R K/% H G A-DDR-KE_ K/% 0.uF nf R0 A_DDR_A A-DDR-A_ A-DDR-RASZ_ /S KE F K/% 0.uF nf A_DDR_A A-DDR-A_ A-DDR-ASZ_ /RAS G N A-DDR-RESET_ A_DDR_A0 A-DDR-A0_ A-DDR-WEZ_ /AS RESET# H A_DDR_WEZ A-DDR-WEZ_ A-DDR-ODT_ /WE G RX RP0 ODT A-DDR_MLK_ A-DDR_MLKZ_ A_DDR_A R R A-DDR-A_ A_DDR_A R R A-DDR-A_ R lose to DRAM 0R_% A_DDR_A A-DDR-A_ A_DDR_A A-DDR-A_ A_DDR_A A-DDR-A_ 0 0 A_DDR_A A-DDR-A_ 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF RX RP0 A_DDR_A A-DDR-A_ 0nF A_DDR_A A-DDR-A_ A A_DDR_A0 A-DDR-A0_ A A_DDR_KE A-DDR-KE_ RX RP MSDA00HTA.0 ustom DDR Thursday, December 0, 0 Date: Sheet of ZQ Q Q Q Q Q R R R R H A A D F F J J L L N N D D

D_FLAG D_SY_OUT PANEL_S PANEL_S D_FLAG D_SY_OUT PANEL_S PANEL_S LVDS ONNETOR N LVDS_ D D M P M P 0 KM KP M_SDA M 0 0 P M_SL M P P M LVDSSEL/D_ON R 0 Panel_rotation R 0R 0M 0 0 0P KP R R KM,, M_SDA M_SL,, 0P R RT_NTL_OUT 0 LVA0P V-Panel V-Panel P LVA0N 0M M P LVAP RT_NTL_IN R 0 0 M P LVAN P 0.uF M LVAP M LVAN KP 0P LVALKP KM 0M LVALKN P N LVDS_ LVAP M DM DP Panel_rotation LVAN P DM DP 0 LVDSSEL/D_ON LVAP M DKM DKP LVAN DP D0P DM LV0P D0M DM 0 0 DP LV0N DP D0M D0P LVP DM D_SY_OUT R0 R LR_SYN LVN DP LVP DM LVN DKP LVLKP DKM LVLKN /PIN DP LVP DM LVN DP LVP DM V-Panel LVN N +V_Normal +.V_Normal R R K K R PANEL_S R 00 Panel_rotation K PANEL_S R 00 LVDSSEL/D_ON D_FLAG R 0R LR_SYN R R K K Date: Thursday, December 0, 0 Sheet of MSDA00HTA ustom LVDS.0

YPPR RA D D N R 0R R0 0R AV-VIDEO YPbPr_Y YPbPr_P VIDEO OUTPUT LINEOUTL N AV_OUT Y Pb AVOUT-V LINEOUTR Pr RA-AV-H R R R R R R YPbPr_PR EARPHONE-OUTL EARPHONE-OUTR.uF.uF 0 LINEOUTL LINEOUTR lose to Mstar I +V_US T L RA-H 0R HD_L HD-AuLin HD-AuRin HD_LIN HD_RIN.K VS_OUT R K 0 R Q0 K R R R R R 0 R R /.K Q AVOUT-V AV RA AV-VIDEO AV-VIDEO AV-AuLin AV-Lin AV-AuRin AV-Rin RAX K K R lose to Mstar I Date: Thursday, December 0, 0 Sheet of MSDA00HTA ustom Video.0 R0 0K R K.uF R 0R HD_R R 0K R N V R R 0K L R 0K R R R

VGA D N D UART_TX R 00R VGA-Rin VGA-Gin VGA-in 00R R UART_RX VGA 0 VGA-in VGA-Gin VGA-Rin R R R R VGA-in VGA-Gin VGA-Rin lose to Mstar I DD_SL_D DD_SDA_D 00R R 00R R UART_RX UART_TX 00R R VGA_VSY 00R R0 VGA_HSY R 0K R 0K Date: Thursday, December 0, 0 Sheet of MSDA00HTA VGA.0 ustom R R

US INTERFAE D D N0 +V_US US-A VUS D- D+ D US_D- US_D+ SHELL SHELL D R.R R.R N0 +V_US US-A VUS D- D+ R0.R US_D- R.R US_D+ SHELL SHELL D0 D US_D- US_D+ US_WIFI N +V_US R.R R.R US0_D- US0_D+ US0_D- US0_D+ US POWER +V_US +V_US +V_US +V_US 0.uF.uF 0.uF.uF 0.uF.uF + A 0uF/V Note: US(N00), usb Note: US(N0), usb Date: Thursday, December 0, 0 Sheet of MSDA00HTA US.0

onnector D D U HST-00SAR MDI_TP MDI_TP TD+ TX+ TX+ DATALED_N TT TX- DATALED_P MDI_TN TX- R0 /% RX+ MDI_TN TD- MT R0 /% TM MT RX- MDI_RP MT LINKLED_P MDI_RP RD+ MT LINKLED_N RX+ RT RJ-LED MDI_RN RX- MDI_RN RD- P R /% REGOUT TM- 0 0 R0 /% nf/kv nf/kv 0nF 0nF Internal PHY +.V_Normal REGOUT MSDA00HTA Ethernet.0 Date: Thursday, December 0, 0 Sheet of ustom 0 R0 0R

HDMI D ON00 D HDMI_RXP HDMI_RXP HDMI/V HDMI_RXN DATA+ HDMI_RXP DATA SHIELD HDMI_RXN HDMI_RXP R0 0R HDMI-RXP HDMI/V HDMI_RXN DATA- HDMI-RXP HDMI_RXP R0 HDMI_RX0P DATA+ HDMI_RXN R 0R HDMI-RXN R0 HDMI_RX0N DATA SHIELD HDMI-RXN HDMI_RXN HDMI_RXP R 0R HDMI-RXP HDMI_LKP DATA- HDMI-RXP HDMI_RX0P R0 R0 HDMI_LKN DATA0+ HDMI_RXN HDMI-RXN DATA0 SHIELD R 0R K HDMI-RXN HDMI_RX0N HDMI_RX0P R 0R HDMI-RX0P HDMI-HPD HDMI-DD-SL DATA0- HDMI-RX0P 0 HDMI_LKP 0K HDMI-DD-SDA LK+ HDMI_RX0N HDMI-RX0N LK SHIELD R 0R Q00 HDMI-RX0N HDMI_LKN HDMI_LKP R 0R HDMI-LKP HDMI-DD-SL 0K 0K R00 R R0.K HDMI-HPDIN D0 D0 D0 D0 LK- HDMI-LKP HDMI-SL D0 D0 D0 D0 HDMI-HPDIN 0 E HDMI-DD-SDA E R0 R HDMI-SDA HDMI_AR HDMI_LKN R 0R HDMI-LKN 0 HDMI-LKN HDMI-DD-SL SL HDMI-DD-SDA SDA DD/E +V POWER HDMI/V ESD 0.pF HDMI-HPD HOT PLUG E & AR HDMI_AR HDMI-AR HDMI-AR.uF E R 00R HDMI-E HDMI-E MSDA00HTA HDMI.0 ustom Thursday, December 0, 0 Date: Sheet of 0 HDMI/0D

SI TUNER AG R Filter &I D +.V_TU D SDA-T R0 00R T_SDA SL-T Y0 R 00R T_SL VDD_.V_OUTPUT R M.000MHz R 0R 0 0 +.V_TU 0.uF 0.uF XTAL_N 0 0 U0 XTAL_P IF_AG 0 0.uF lose Tuner IF_AG_T _XTAL VDD_p_ RESET_N AS /0.uF R 00R LK_OUT VDD_p_ SDA-T SDA LNA_INP ohm Line nf WSA0TF T0 J0 nf F onn 0 L0.nH SL-T SL LNA_INN RF MxL0 L0 nf 0nH TUNER POWER +.V_TU VDD_.V_OUTPUT 0.uF.nF L0 VDD_IO VDD_p_ 0nH IF_AG_DM R 00R TP AG_/GPO _DIG nf nf 0.uF U 0 0.uF AG_ VDD_p AMS-. IF_AG R 00R 0.nF +.V_Normal V_TU 0.uF V_TU R0 0R IN OUT ADJ VDD_p_ VDD_p_ IF_OUTP_ IF_OUTN_ IF_OUTP_/GPO_ IF_OUTN_/GPO_ 0 +V_Normal 0 0.uF 0uF 0.uF TUNER POWER J VDD_.V_OUTPUT 0 0.uF 0.uF 0.uF uf +.V_TU V_TU +.V_TU 0 0uF nf SHIELD DIF IN&OUT VIFM VIFM R 00R IF-IN+ IF-IN- IF-IN- IF-IN+ 00pF VIFP VIFP R 00R 00pF MSDA00HTA Tuner.0 Thursday, December 0, 0 Date: Sheet of

D D +V_NORMAL +V_amp L F AMP 0 0.uF 0uF/V 0.uF 0.uF 0 0 0uF/V R..uF 0.uF V_Normal R..uF 0.uF V_Normal V_Normal L0 F +.V_Normal 0 U IS_MLK IS_MLK R AMP-Lout- IS_SLK IS_SLK R0 MLK OUT_A 0 L IS_LRLK IS_LRLK R SLK 0 00nF/V uh 0 IS_SD0 IS_SD0 R LRLK ST_A 0nF 0nF SDIN ST_ 00nF/V,, M_SL R,, M_SDA R SL AMP-Lout+ HP_MUTE_AMP SDA 0nF TAS0L OUT_ 0nF L PDN uh 0 uf/v 00pF VLAMP_A R 0 nf PLL_FLTP V_Normal VLAMP_D uf/v 0.0uF VR_ANA R0 R0 00pF 0 AMP-Rout- R 0 nf PLL_FLTM OUT_ L R R 00R/% uh OS_RES ST_ 00nF/V K 0nF 0nF K/%.uF 00nF/V VR_DIG ST_D 0.uF AMP-Rout+ R /00pF K SSTIMER OUT_D 0nF 0nF L O_ADJ VREG uh FAULT RESET V_Normal N R 0K 0.uF/V Speaker AMP-Rout+ R0 R RST_AMP R 00 AMP-Rout- 0K AMP-Lout- AMP-Lout+ 0.uF MUTE ircuit +V_Standby R /0 AMP-MUTE AMP-MUTE 0: Normal Mute R 0K R 00 +V_NORMAL +V_Normal R 0K HP_MUTE_AMP D /AV R /M Q /0 R /K Q /0 SOT PWD_MT R E /K SOT R /00 R0 E R R /K /.uf A /.M /00 A 0 /0uF/V 0 /.uf EN=HIGH: OPERATING EN=LOW MUTE MSDA00HTA Amplify.0 ustom Date: Thursday, December 0, 0 Sheet of 0 P_A P_A P_D P_D DO A D A STEST EPAD PV_A PV_A PV_ PV_ PV_D 0 PV_D AV PV AVDD DVDD R E Q 0 SOT

inand FLASH U00 NF_LK W EMM_D NF_MD LK D J W EMM_D EMM_D0 MD D J H EMM_D EMM_D D0 D J H EMM_D EMM_D D D J H EMM_D D J NF_RSTZ D D RESET U D NF_POWER VDD M VDD N VDD T0 VDD U 00.uF NF_POWER +.V_Normal NF_POWER 00 0.uF NF_POWER 00 0.uF 00 0.uF EMM_D EMM_D EMM_D EMM_D EMM_D EMM_D EMM_D EMM_D0 NAND_ALE NAND_WPZ NAND_EZ NAND-EZ NAND_LE NAND_REZ NAND_WEZ NAND_RZ NAND_ALE NAND_WPZ NAND_EZ NAND-EZ NAND_LE NAND_REZ NAND_WEZ NAND_RZ EMM_D0 R0 0K NF_MD EMM_MD EMM_D R0 0K EMM_MD NF_RSTZ EMM_RSTZ EMM_D R0 0K EMM_RSTZ NF_LK R00 R EMM_LK EMM_D R0 0K EMM_LK EMM_D R0 0K 00 EMM_D R0 0K EMM_D R0 0K /pf EMM_D R0 0K NF_MD R00 0K NAND FLASH +.V_Normal NAND_FLASH_PWR-.V U000 /MTFG0AA NAND_FLASH_PWR-.V 0/V / / PM_A D PM_A NAND-RZ /R/ D PM_A NAND-REZ R/ D PM_A NAND-EZ RE D NAND-ALE NAND_ALE NAND_ALE NAND-EZ E 0 0 NAND-WPZ NAND_WPZ /E NAND_WPZ NAND-EZ NAND_EZ /V R0 /0R NAND_EZ NAND-EZ NAND-EZ V V NAND-LE NAND_LE NAND-EZ NAND_LE Micron Nand NAND-REZ NAND_REZ NAND_REZ NAND-WEZ NAND_WEZ NAND_WEZ NAND-LE 0/V NAND-RZ NAND_RZ NAND_RZ NAND-ALE LE PM_A NAND-WEZ ALE D PM_A NAND-WPZ WE D PM_A WP D 0 0 PM_A0 0 D0 A A / /V / 00 /0.uF 00 /0.uF PM_A[:0] PM_A[:0] ustom Date: Thursday, December 0, 0 Sheet of MSxxx PMIA & NAND.0 inand K W Y AA AA K Y Y AA AA VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF REG/VDDi KLMGHEF-00 M P R0 U K 00.uF

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关. 接线图 序号 名称专用号规格 单耗 交流电源线 交流电源线 00000A 电源线开关总成 0mm/00mm 船型开关 N LVDS 线 0000 FI-REHL/0/00-*Y- 电源板 机芯供电线 0000 SH00-Y/0/SH00-Y N N N WR WIFI 小板 WR WIFI 信号线 0000A H00-P/0/H00-P 喇叭及喇叭线 0000 喇叭 YXMK-0W- Ω-A-WS ON A ~0V WR 交流开 您正在使用 ZWAD 00i 试用版详情请查阅 WWW.ZWAD.OM 0000-P/0/H00 遥控信号线 00000 -P/0/H00-P 0本控线 0000 00H00-P/0/H00-P N N WR0 WR A00 WR WR T-ON 板 媒体编号 电源线音视频信号线 控制信号线崔志龙接线图 A 胡希嘉 阶段 青岛海尔电子有限公司云电视经营体 WR P 扬声器扬声器 LDU000/WS N N N N N 本控板 WR 装饰灯遥控板 备注 :U000 系列有 WiFi U00/U00 系列无 WiFi 徐一龙张明