目录 一 产品简介 产品概述 应用场景... 4 二 产品规格... 5 三 接口描述... 7 四 接口定义... 9 五 附录 源码获叏 联系我们

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1 Core-3399J 核心板 产品规格书 作者 天启智能科技有限公司 版本 V1.1 日期 版本更新日期更新内容 V 原始版本 V 精简了 V1.0 版本里的 参考设计 相关内容 广东省中山市东区中山四路 57 号宏宇大厦 1 座 全国服务热线 电话

2 目录 一 产品简介 产品概述 应用场景... 4 二 产品规格... 5 三 接口描述... 7 四 接口定义... 9 五 附录 源码获叏 联系我们 广东省中山市东区中山四路 57 号宏宇大厦 1 座 全国服务热线 电话

3 公司简介 天启智能科技有限公司, 成立于 2005 年, 拥有超过十年科技产品的研収经验, 拥有 6 项収明与利不 30 多项计算机软件著作权, 是国家高新技术企业 我们与注于开源智能硬件, 物联网 数字音频产品的研収设计 生产和销售, 同时提供了智能硬件产品的整体解决方案 Firefly 是旗下的品牉, 经营开源产品 开源社区不网上商城, 拥有庞大的企业用户不开収者用户, 产品深叐用户好评 Firefly 开源产品包括开源板 核心板 行业主板等 开源板系列是芯片原厂瑞芯微 (Rockchip) 推荐板卡, 获得原生 SDK 支持 核心板不行业主板广泛应用于商业显示 广告一体机 智能 POS 人脸识别终端 物联网 智慧城市等领域 目前已有超过 10 万用户, 包括 2000 多家的企业用户, 知名用户有 ARM Google 百度 腾讯 阿里巴巴等 Firefly 团队研収成员超过 60 人, 拥有原理图设计 PCB Layout 主板 量产 嵌入式开収 系统开収 应用程序开収等研収能力, 为众多科技创业者 不初创企业加速研収进程, 并提供与业的技术服务 让科技更简单, 让生活更智能 是 Firefly 团队的理念, 我们希望能通 过 Firefly 的开源产品不技术服务, 让各种科技产品的研収发得高效简单, 让 智能科技融入生活 广东省中山市东区中山四路 57 号宏宇大厦 1 座 全国服务热线 电话

4 一 产品简介 1 产品概述 Core-3399J 是 Firefly 团队精心打造的一款核心板, 采用瑞芯微 RK3399 六核 64 位 ( A72x2+A53x4 ) 主频高达 2.0GHz 支持多路显示: 双 MIPI HDMI edp DisplayPort 显示接口, 支持双屏同显 双屏异显 支持多种网络接口 : 双频 WIFI Bluetooth4.1 千兆以太网 Mini PCIE( 扩展 3G/4G 通讯模块 ) 拥有高性能外设接口 :1 USB3.0 接口 1 x PCIe M.2(M-Key) 接口, 可用于扩展 NVMe SSD 核心板采用 10 层布线工艺, 设计尺寸仅有 82mm x 63mm, 性能稳定可靠, 适合丌同的应用环境 拥有完善的系统软件 : 支持 Android Linux Ubuntu 等系统, 支持 Phoenix Flint OS 桌面版办公系统, 开放源代码适合企业二次开収, 可降低研収门槛, 缩短产品研収周期 2 应用场景 高性能计算 / 存储计算机视觉游艺游戏设备商显一体设备 医疗健康设备自劢售货机智能 POS 机互劢打印机 广东省中山市东区中山四路 57 号宏宇大厦 1 座 全国服务热线 电话

5 二 产品规格 类型 规格参数 CPU 型号 Rockchip RK3399 (28 纳米 HKMG 制程 ) 处理器 ARM 六核 64 位处理器, 主频高达 2.0GHz 基于 big. LITTLE 大小核架构, 双核 Cortex-A72( 大核 )+ 四核 Cortex-A53( 小核 ) ARM Mali-T860 MP4 四核 GPU 图形处理器 支持 OpenGL ES1.1/2.0/3.0/3.1, OpenVG1.1, OpenCL, DX11 支持 AFBC( 帧缓冲压缩 ) 支持 4K VP9 and 4K 10bits H265/H264 视频解码, 高达 60fps 视频处理器 1080P 多格式视频解码 (WMV, MPEG-1/2/4, VP8) 1080P 视频编码, 支持 H.264,VP8 格式 视频后期处理器 : 反交错 去噪 边缘 / 细节 / 色彩优化 电源管理 RK808(PMU) 内存 2GB 双通道 64Bit DDR3-1333MHz (1GB/2GB/4GB 可选配 ) 存储器 8GB 高速 emmc 5.1 (8GB/16GB/32GB/128GB 可选配 ) RTC 内置 RTC 实时时钟 ( 支持定时开关机 ) 系统 Android 7.1 / Ubuntu / Linux ( 官方 ) Flint OS ( 合作 ) 电源 输入电压 5V, 峰值电流 3A 无线网络 带 SDIO 接口, 用于扩展 WiFi& 蓝牊二合一模块 以太网 集成 GMAC 以太网控制器 支持扩展 Realtek RTL8211E 实现 10/100/1000Mbps 以太网 广东省中山市东区中山四路 57 号宏宇大厦 1 座 全国服务热线 电话

6 视频输出接口 : - 1 x HDMI 2.0, 支持 4K@60fps 输出和 HDCP 1.4/2.2 显示 - 1 x DP 1.2 (DisplayPort), 支持 4K@60fps 输出 显示屏接口 ( 支持双屏同显 双屏异显 ): - 1 x MIPI-DSI, 支持双通道 2560x1600@60fps 输出 - 1 x edp 1.3 ( 4 lanes with 10.8Gbps ) 1 x HDMI 2.0 和 1 x DP 1.2 ( DisplayPort ), 音频输出 音频 1 x SPDIF 数字音频接口, 用于音频输出 3 x I2S 用于音频输入输出, ( 其中 I2S0/I2S2 支持 8 通道输入 / 输出,I2S2 内部提供给 HDMI/DP 音频输出 ) 摄像头 2 x MIPI-CSI 摄像头接口 ( 内置双硬件 ISP, 最高支持单 13Mpixel 戒双 8Mpixel ) 1 x DVP 摄像头接口 ( 最高支持 5Mpixel) USB 2 x USB2.0 Host,2 x USB3.0 扩展接口 SDMMC I2C I2S SPI UART ADC PWM GPIO 核心板尺寸 82mm x 63mm( 板厚 1.2mm) 接口类型 MXM3.0 (314 PIN, 0.5mm 间距 ) PCB 规格 8 层板设计, 沉金工艺 重量 24 克 广东省中山市东区中山四路 57 号宏宇大厦 1 座 全国服务热线 电话

7 三 接口描述

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9 四 接口定义 PIN Core board pin definition Default function Defual function description Pad type IO Pull 1 VCC_SYS VCC_SYS Input Voltage 5V 2 GND GND GND 3 VCC_SYS VCC_SYS Input Voltage 5V 4 GND GND GND 5 VCC_SYS VCC_SYS Input Voltage 5V 6 GND GND GND 7 VCC_SYS VCC_SYS Input Voltage 5V 8 GND GND GND 9 VCC_SYS VCC_SYS Input Voltage 5V 10 GND GND GND 11 VCC_SYS VCC_SYS Input Voltage 5V 12 GND GND GND 13 VCC_SYS VCC_SYS Input Voltage 5V 14 GND GND GND 15 VCC_SYS VCC_SYS Input Voltage 5V 16 GND GND GND 17 VCC_SYS VCC_SYS Input Voltage 5V 18 GND GND GND 19 GND GND GND 20 VCC3V3_SYS VCC3V3_SYS Input Voltage 5V 21 MAC_CLK GPIO3_B3/MAC_CLK/I2C5_SCL MAC reference clock output I2C serial port 4,need external pull-up 22 VCC3V3_SYS VCC3V3_SYS Output Voltage 3.3V I/O UP

10 23 PHY_RST GPIO3_B7/MAC_CRS/UART3_RX MAC carrier sense detect I/O UP 24 VCC3V3_SYS VCC3V3_SYS Output Voltage 3.3V 25 PHY_PMEB GPIO0_A1/DDRIO_PWROFF/TCPD_CCDB_E SDMMC0 power control output I/O UP 26 VCC3V3_S3 VCC3V3_S3 Output Voltage 3.3V 27 MAC_MDIO GPIO3_B5/MAC_MDIO/UART1_TX MAC management command and data PCIE reset input 28 VCC3V3_S3 VCC3V3_S3 Output Voltage 3.3V 29 MAC_MDC GPIO3_B0/MAC_MDC/SPI0_CSN1 MAC management clock I/O UP 30 VCC3V3_S3 VCC3V3_S3 Output Voltage 3.3V 31 PHY_INT GPIO3_B2/MAC_RXER/I2C5_SDA MAC receive error I2C serial port 4,need external pull-up 32 GND GND GND 33 GND GND GND 34 VCC_3V0 VCC_3V0 Output Voltage 3.0V 35 PHY_TXEN GPIO3_B4/MAC_TXEN/UART1_RX MAC transmit enable AP wake up PCIE I/O UP 36 VCC_3V0 VCC_3V0 Output Voltage 3.0V 37 PHY_TXD3 GPIO3_A1/MAC_TXD3/SPI4_TXD MAC transmit data I/O DOWN 38 VCC_1V8 VCC_1V8 Output Voltage 1.8V 39 PHY_TXD2 GPIO3_A0/MAC_TXD2/SPI4_RXD MAC transmit data I/O DOWN 40 VCC_1V8 VCC_1V8 Output Voltage 1.8V 41 PHY_TXD1 GPIO3_A5/MAC_TXD1/SPI0_TXD MAC transmit data I/O DOWN 42 VCC_RTC VCC_RTC Input Voltage 5V 43 PHY_TXD0 GPIO3_A4/MAC_TXD0/SPI0_RXD MAC transmit data I/O DOWN 44 VCCA1V8_S3 VCCA1V8_S3 45 PHY_TXCLK GPIO3_C1/MAC_TXCLK/UART3_RTSN MAC transmit clock I/O UP 46 GND GND GND 47 GND GND GND I/O I/O UP UP

11 48 EDP_AUXN EDP_AUXN edp differential AUX channel positive output Output (1.8V) 49 MAC_RXDV GPIO3_B1/MAC_RXDV MAC receive data valid I/O DOWN 50 EDP_AUXP EDP_AUXP edp differential AUX channel negative output Output (1.8V) 51 MAC_RXD0 GPIO3_A6/MAC_RXD0/SPI0_CLK MAC receive data I/O UP 52 GND GND GND 53 MAC_RXD1 GPIO3_A7/MAC_RXD1/SPI0_CSN0 MAC receive data I/O UP 54 EDP_TX0N EDP_TX0N edp differential lane 0 negative output Output (1.8V) 55 MAC_RXD2 GPIO3_A2/MAC_RXD2/SPI4_CLK MAC receive data I/O UP 56 EDP_TX0P EDP_TX0P edp differential lane 0 positive output Output (1.8V) 57 MAC_RXD3 GPIO3_A3/MAC_RXD3/SPI4_CSN0 MAC receive data I/O UP 58 GND GND GND 59 MAC_RXCLK GPIO3_B6/MAC_RXCLK/UART3_TX MAC receive clock I/O UP 60 EDP_TX1N EDP_TX1N edp differential lane 1 negative output Output (1.8V) 61 GND GND GND 62 EDP_TX1P EDP_TX1P edp differential lane 1 positive output Output (1.8V) 63 GPIO2_B4/DVP_PDN0_H GPIO2_B4/SPI2_CSN0 Camera power down control output for front I/O UP 64 GND GND GND 65 GPIO2_A0/CIF_D0 GPIO2_A0/VOP_D0/CIF_D0/I2C2_SDA Camera data port I/O UP 66 EDP_TX2N EDP_TX2N edp differential lane 2 negative output Output (1.8V) 67 GPIO2_A1/CIF_D1 GPIO2_A1/VOP_D1/CIF_D1/I2C2_SCL Camera data port I/O UP 68 EDP_TX2P EDP_TX2P edp differential lane 2 positive output Output (1.8V) 69 GPIO2_A2/CIF_D2 GPIO2_A2/VOP_D2/CIF_D2 Camera data port I/O DOWN 70 GND GND GND 71 GPIO2_A3/CIF_D3 GPIO2_A3/VOP_D3/CIF_D3 Camera data port I/O DOWN 72 EDP_TX3N EDP_TX3N edp differential lane 3 negative output Output (1.8V) 73 GPIO2_A4/CIF_D4 GPIO2_A4/VOP_D4/CIF_D4 Camera data port I/O DOWN 74 EDP_TX3P EDP_TX3P edp differential lane 3 positive output Output (1.8V)

12 75 GPIO2_A5/CIF_D5 GPIO2_A5/VOP_D5/CIF_D5 Camera data port I/O DOWN 76 GND GND GND 77 GPIO2_A6/CIF_D6 GPIO2_A6/VOP_D6/CIF_D6 Camera data port I/O DOWN 78 SPDIF_TX GPIO3_C0/MAC_COL/UART3_CTSN MAC collision detect I/O UP 79 GPIO2_A7/CIF_D7 GPIO2_A7/VOP_D7/CIF_D7/I2C7_SDA Camera data port I/O UP 80 GND GND GND 81 GPIO2_B1/CIF_HREF GPIO2_B1/SPI2_RXD/CIF_HREF/I2C6_SDA Camera href input I2C serial port 6,for battery, need external pull up 82 TP_RST GPIO0_B4/TCPD_VBUS_BDIS Type-C0 discharge control I/O DOWN 83 GPIO2_B0/CIF_VSYNC GPIO2_B0/VOP_CLK/CIF_VSYNC/I2C7_SCL Camera vsync input I/O UP 84 SDMMC0_DET_L GPIO0_A7/SDMMC0_DET SDMMC0 detect input I/O UP 85 GND GND GND 86 SDMMC0_D2 GPIO4_B2/SDMMC0_D2/APJTAG_TCK SDMMC0 data port JTAG TCK for AP I/O UP 87 GPIO2_B2/CIF_CLKI GPIO2_B2/SPI2_TXD/CIF_CLKIN/I2C6_SCL Camera clock input I2C serial port 6,for battery, need external pull up 88 SDMMC0_D3 GPIO4_B3/SDMMC0_D3/APJTAG_TMS SDMMC0 data port JTAG TMS for AP I/O UP 89 GPIO2_B3/CIF_CLKO GPIO2_B3/SPI2_CLK/VOP_DEN/CIF_CLKOUT Camera clock output I/O UP 90 SDMMC0_CMD GPIO4_B5/SDMMC0_CMD/MCUJTAG_TMS SDMMC0 command output JTAG TMS for MCU I/O UP 91 GND GND GND 92 SDMMC0_CLK GPIO4_B4/SDMMC0_CLKOUT/MUCJTAG_TC K SDMMC0 clock output JTAG TCK for MCU 93 VCC1V8_DVP VCC1V8_DVP Output Voltage 1.8V 94 SDMMC0_D0 GPIO4_B0/SDMMC0_D0/UART2DBG_RX SDMMC0 data port I/O UP 95 VCC2V8_DVP VCC2V8_DVP Output Voltage 2.8V 96 SDMMC0_D1 GPIO4_B1/SDMMC0_D1/UART2DBG_TX SDMMC0 data port I/O UP 97 VCCA VCCA Input Voltage 3V-5V 98 BL_EN GPIO1_A1/ISP_SHUTTER_TRIG/TCPD_CC0_ COMP Sersor interrupt Charge ok input I/O DOWN I/O I/O I/O UP UP DOWN

13 VCONN_EN 99 SPI1_RXD/GPIO1_A7_U GPIO1_A7/SPI1_RXD/PMCU_UART4DBG_RX SPI bus port 1, for FW boot Uart4 serial port data input, for PMCU debug 100 LCD_EN GPIO1_A4/ISP_PRELIGHT_TRIG ISP_PRELIGHT_TRIG I/O DOWN 101 SPI1_TXD/GPIO1_B0_U GPIO1_B0/SPI1_TXD/PMCU_UART4DBG_TX SPI bus port 1, for FW boot Uart4 serial port data output, for PMCU debug 102 VCC5V0_TYPEC0_EN GPIO1_A3/ISP_FLASHTRIGOUT ISP_FLASHTRIGOUT I/O DOWN 103 SPI1_CLK/GPIO1_B1_U GPIO1_B1/SPI1_CLK/PMCU_JTAG_TCK SPI bus port 1, for FW boot JTAG TCK for PMCU I/O UP 104 VCC5V0_HOST_EN GPIO1_A0/ISP_SHUTTER_EN/TCPD_VBUS_S INK_EN Hall sensor interrupt input COMP Sersor interrupt I/O DOWN 105 SPI1_CSN0/GPIO1_B2_U GPIO1_B2/SPI1_CSN0/PMCU_JTAG_TMS SPI bus port 1, for FW boot JTAG TMS for PMCU I/O UP 106 TYPEC0_U2VBUSDET TYPEC0_U2VBUSDET TYPEC0 connected / vbus power detect for USB GND GND GND 108 TYPEC1_U2VBUSDET TYPEC1_U2VBUSDET TYPEC1 connected / vbus power detect for USB PCIE_REF_CLKP PCIE_RCLK_100M_P PCIE 100MHz reference clock as input to PLL 110 CIF_PWR GPIO1_C6/DFTJTAG_TDI/TCPD_VBUS_SOUR CE0 G-sensor interrupt input I/O DOWN 111 PCIE_REF_CLKN PCIE_RCLK_100M_N PCIE 100MHz reference clock as input to PLL 112 DVP_PWR GPIO1_C7/DFTJTAG_TDO/TCPD_VBUS_SOU RCE1 113 GND GND GND Adapter insert detect input I/O DOWN 114 GPIO2_D4_D/DVP_PDN1 GPIO2_D4/SDIO0_BKPWR Camera power down control output for rear I/O DOWN 115 PCIE_TX0N PCIE_TX_0N PCIE differential lane 0 negative output 116 HP_DET ADC_IN4 VDD_GPU voltage detect input 117 PCIE_TX0P PCIE_TX_0P PCIE differential lane 0 positive output 118 FAN_INT ADC_IN3 DRAM ID detect input 119 GND GND GND I/O I/O UP UP

14 120 ADC_IN0 ADC_IN0 Battery voltage input Board ID detect input 121 PCIE_RX0_N PCIE_RX_0N PCIE differential lane 0 negative input 122 RECOVER ADC_IN1 AD keyboard input 123 PCIE_RX0_P PCIE_RX_0P PCIE differential lane 0 positive input 124 ADC_IN2 ADC_IN2 Headphone 125 GND GND GND 126 GND GND GND 127 PCIE_TX1N PCIE_TX_1N PCIE differential lane 1 negative output 128 HOST1_DM HOST1_DM USB HOST1 Data Minus port 129 PCIE_TX1P PCIE_TX_1P PCIE differential lane 1 positive output 130 HOST1_DP HOST1_DP USB HOST1 Data Plus port 131 GND GND GND 132 GND GND GND 133 PCIE_RX1_N PCIE_RX_1N PCIE differential lane 1 negative input 134 HOST0_DM HOST0_DM USB HOST0 Data Minus port 135 PCIE_RX1_P PCIE_RX_1P PCIE differential lane 1 positive input 136 HOST0_DP HOST0_DP USB HOST0 Data Plus port 137 GND GND GND 138 GND GND GND 139 PCIE_TX2N PCIE_TX_2N PCIE differential lane 2 negative output 140 TYPEC1_SBU1 TYPEC1_AUXP TYPEC1 AUX differential TX/RX serial data 141 PCIE_TX2P PCIE_TX_2P PCIE differential lane 2 positive output 142 TYPEC1_SBU2 TYPEC1_AUXM TYPEC1 AUX differential TX/RX serial data. 143 GND GND GND 144 GND GND GND 145 PCIE_RX2_N PCIE_RX_2N PCIE differential lane 2 negative input 146 TYPEC1_TX2N TYPEC1_TX2M TYPEC1 negative half of second Super Speed

15 TX differential pair. 147 PCIE_RX2_P PCIE_RX_2P PCIE differential lane 2 positive input 148 TYPEC1_TX2P TYPEC1_TX2P 149 GND GND GND 150 GND GND GND TYPEC1 positive half of second Super Speed TX differential pair. 151 PCIE_TX3N PCIE_TX_3N PCIE differential lane 3 negative output 152 TYPEC1_RX2P TYPEC1_RX2P TYPEC1 positive half of second Super Speed RX differential pair 153 PCIE_TX3P PCIE_TX_3P PCIE differential lane 3 positive o 154 TYPEC1_RX2N TYPEC1_RX2M 155 GND GND GND 156 GND GND GND TYPEC1 negative half of second Super Speed RX differential pair 157 PCIE_RX3_N PCIE_RX_3N PCIE differential lane 3 negative input 158 TYPEC1_SBU1_DC TYPEC1_AUXP_PD_PU TYPEC1 AUX pull-up/pull-down polarity reversal pins. 159 PCIE_RX3_P PCIE_RX_3P PCIE differential lane 3 positive input 160 TYPEC1_SBU2_DC TYPEC1_AUXM_PU_PD TYPEC1 AUX pull-up/pull-down polarity reversal pins. 161 GND GND GND 162 USB3_SSTXN TYPEC1_TX1M TYPEC1 negative half of first Super Speed TX differential pair 163 PCIE_PWR_EN GPIO1_C1/SPI3_CLK CPU Power sleep enable control I/O DOWN 164 USB3_SSTXP TYPEC1_TX1P TYPEC1 positive half of first Super Speed TX differential pair. 165 TP_INT GPIO1_C4/I2C8_SDA Touch pannel interrupt input I/O UP 166 USB3_SSRXP TYPEC1_RX1P TYPEC1 positive half of first Super Speed RX differential pair

16 167 I2C4_SDA GPIO1_B3/I2C4_SDA I2C serial port 4,for MEMS, need external pull up I/O UP 168 USB3_SSRXN TYPEC1_RX1M TYPEC1 negative half of first Super Speed RX differential pair 169 I2C4_SCL GPIO1_B4/I2C4_SCL I2C serial port 4,for MEMS, need external pull up I/O UP 170 USB3_DP TYPEC1_DP TYPEC1 Data Plus port 171 PWR_EN PWR_EN System power enable signal input 172 USB3_DM TYPEC1_DM TYPEC1 Data Minus port 173 POWER_ON POWER_ON Power on Signal Input 174 TYPEC0_TX2N TYPEC0_TX2M 175 CPU_DET GPIO1_D0/DFTJTAG_CLK/TCPD_VBUS_SOU RCE2 176 TYPEC0_TX2P TYPEC0_TX2P 177 IR_INT GPIO0_A6/PWM3A_IR 178 TYPEC0_RX2P TYPEC0_RX2P 179 DIY_LED GPIO0_B5/TCPD_VBUS_SOURCE3/TCPD_VB US_FDIS 180 TYPEC0_RX2N TYPEC0_RX2M TYPEC0 negative half of second Super Speed TX differential pair Gyroscope interrupt input FUSB302 interrupt input for Type-C1 TYPEC0 positive half of second Super Speed TX differential pair Power dynamic voltage scaling control for CENTERLOGIR receiver input TYPEC0 positive half of second Super Speed RX differential pair. I/O I/O DOWN DOWN Type-C1 discharge control Hall Sersor interrupt input I/O DOWN TYPEC0 negative half of second Super Speed RX differential pair 181 RESET_L RESET Input system reset signal 182 TYPEC0_DM TYPEC0_DM TYPEC0 Data Minus port 183 3G_PWR_EN GPIO0_A2/WIFI_26MHZ 26MHz clock output I/O DOWN 184 TYPEC0_DP TYPEC0_DP TYPEC0 Data Plus port 185 MIPI_RST GPIO0_B0/SDMMC0_WRPT/TEST_CLKOUT2 DVP power enable I/O UP

17 186 TYPEC0_TX1N TYPEC0_TX1M TYPEC0 negative half of first Super Speed TX differential pair. 187 PWR_KEY_L GPIO0_A5/EMMC_PWRON Power key detect input I/O UP 188 TYPEC0_TX1P TYPEC0_TX1P TYPEC0 positive half of first Super Speed TX differential pair. 189 WORK_LED GPIO2_D3/SDIO0_PWREN MIPI camera reset output MEMSl interrupt input I/O DOWN 190 TYPEC0_RX1P TYPEC0_RX1P TYPEC0 positive half of first Super Speed RX differential pair 191 HDMI_CEC GPIO4_C7/HDMI_CECINOUT/EDP_HOTPLUG HDMI CEC communication I/O UP 192 TYPEC0_RX1N TYPEC0_RX1M 193 PORT_HPD HDMI_HPD TYPEC0 negative half of first Super Speed RX differential pair. HDMI Hot Plug Detection interrupt with 5V tolerance 194 TYPEC0_SBU1 TYPEC0_AUXP TYPEC0 AUX differential TX/RX serial data. 195 I2C3_SCL_HDMI GPIO4_C1/I2C3_SCL_HDMI/UART2DBG_TX I2C serial port 3,for HDMI, need external pull-up I/O UP 196 TYPEC0_SBU2 TYPEC0_AUXM TYPEC0 AUX differential TX/RX serial data. 197 I2C3_SDA_HDMI GPIO4_C0/I2C3_SDA_HDMI/UART2DBG_RX I2C serial port 3,for HDMI, need external pull-up I/O UP 198 TYPEC0_SBU2_DC TYPEC0_AUXM_PU_PD TYPEC0 AUX pull-up/pull-down polarity reversal pins. 199 CHG_CC_INT_L GPIO1_A2/ISP_FLASHTRIGIN/TCPD_CC1_VC ONN_EN 200 TYPEC0_SBU1_DC TYPEC0_AUXP_PD_PU Charge and cc controler interrupt input I/O DOWN TYPEC0 AUX pull-up/pull-down polarity reversal pins. 201 RTC_CLK_OUT RTC_CLK_OUT RTC_CLK_OUT 202 GND GND GND 203 GND GND GND 204 HDMI_TX2P HDMI_TX2P HDMI channel 2 differential serial data positive 205 BT_HOST_WAKE_L GPIO0_A4/SDIO0_INTn BT module wake up AP I/O DOWN

18 206 HDMI_TX2N HDMI_TX2N HDMI channel 2 differential serial data negative 207 BT_WAKE_L GPIO2_D2/SDIO0_DETN/PCIE_CLKREQN AP wake up BT module I/O UP 208 HDMI_TX1P HDMI_TX1P HDMI channel 1 differential serial data positive 209 UART0_RTS GPIO2_C3/UART0_RTSN UART0 serial port, for BT module I/O UP 210 HDMI_TX1N HDMI_TX1N HDMI channel 1 differential serial data negative 211 UART0_CTS GPIO2_C2/UART0_CTSN UART0 serial port, for BT module I/O UP 212 HDMI_TX0P HDMI_TX0P HDMI channel 0 differential serial data positive 213 UART0_TXD GPIO2_C1/UART0_TX UART0 serial port, for BT module I/O UP 214 HDMI_TX0N HDMI_TX0N HDMI channel 0 differential serial data negative 215 UART0_RXD GPIO2_C0/UART0_RX UART0 serial port, for BT module I/O UP 216 HDMI_TXCP HDMI_TCP HDMI differential pixel clock positive 217 BT_REG_ON_H GPIO0_B1/PMUIO2_1833_VOLSEL BT module power enable I/O DOWN 218 HDMI_TXCN HDMI_TCN HDMI differential pixel clock negative 219 SDIO0_D1 GPIO2_C5/SDIO0_D1/SPI5_TXD SDIO0 data port,for WIFI module I/O UP 220 GND GND GND 221 SDIO0_D0 GPIO2_C4/SDIO0_D0/SPI5_RXD SDIO0 data port,for WIFI module I/O UP 222 MIPI_TX0_D0P MIPI_TX0_D0P MIPI-DSI0 differential lane 0 positive 223 SDIO0_D2 GPIO2_C6/SDIO0_D2/SPI5_CLK SDIO0 data port,for WIFI module I/O UP 224 MIPI_TX0_D0N MIPI_TX0_D0N MIPI-DSI0 differential lane 0 negative 225 SDIO0_D3 GPIO2_C7/SDIO0_D3/SPI5_CSN0 SDIO0 data port,for WIFI module I/O UP 226 GND GND GND 227 SDIO0_CLK GPIO2_D1/SDIO0_CLKOUT/TEST_CLKOUT1 SDIO0 clock output, for WIFI module I/O UP 228 MIPI_TX0_D1P MIPI_TX0_D1P MIPI-DSI0 differential lane 1 positive 229 SDIO0_CMD GPIO2_D0/SDIO0_CMD SDIO0 command output,for WIFI module I/O UP 230 MIPI_TX0_D1N MIPI_TX0_D1N MIPI-DSI0 differential lane 1 negative 231 WIFI_HOST_WAKE_L GPIO0_A3/SDIO0_WRPT WIFI module wake up AP I/O DOWN 232 GND GND GND

19 233 WIFI_REG_ON_H GPIO0_B2 WIFI module power enable I/O DOWN 234 MIPI_TX0_CLKP MIPI_TX0_CLKP MIPI-DSI0 differential clock lane positive 235 GND GND GND 236 MIPI_TX0_CLKN MIPI_TX0_CLKN MIPI-DSI0 differential clock lane negative 237 RTC_CLKO_WIFI RTC_CLKO_WIFI RTC_CLKO_WIFI 238 GND GND GND 239 EXT_EN EXT_EN EXT_EN 240 MIPI_TX0_D2P MIPI_TX0_D2P MIPI-DSI0 differential lane 2 positive 241 OTP_RST OTP_RST OTP_RST 242 MIPI_TX0_D2N MIPI_TX0_D2N MIPI-DSI0 differential lane 2 negative 243 TYPEC1_ID TYPEC1_ID 244 GND GND 245 TYPEC0_ID TYPEC0_ID TYPEC1 ID detect input,200kohm internal pull up to USB_AVDD_1V8 TYPEC0 ID detect input,200kohm internal pull up to USB_AVDD_1V8 246 MIPI_TX0_D3P MIPI_TX0_D3P MIPI-DSI0 differential lane 3 positive 247 TP_INT1 GPIO4_D4 Headphone insert detect input I/O DOWN 248 MIPI_TX0_D3N MIPI_TX0_D3N MIPI-DSI0 differential lane 3 negative 249 LCD_RST GPIO4_D5 LCD panel CABC enable LCD panel reset output I/O DOWN 250 GND GND GND 251 UART2DBG_TX GPIO4_C4/UART2DBG_TX Uart2 serial port data output,for AP debug I/O UP 252 MIPI_RX0_D0P MIPI_RX0_D0P MIPI-CSI0 differential lane 0 positive 253 UART2DBG_RX GPIO4_C3/UART2DBG_RX Uart2 serial port data input, for AP debug I/O UP 254 MIPI_RX0_D0N MIPI_RX0_D0N MIPI-CSI0 differential lane 0 negative 255 PCIE_DISABLE GPIO4_D3 EFUSE VPQS power control output I/O DOWN 256 GND GND GND 257 PCIE_CLKREQ GPIO4_D0/PCIE_CLKREQN ALS sensor interrupt input I/O UP

20 258 MIPI_RX0_D1P MIPI_RX0_D1P MIPI-CSI0 differential lane 1 positive 259 PCIE_RST PCIE_RST PCIE_RST 260 MIPI_RX0_D1N MIPI_RX0_D1N MIPI-CSI0 differential lane 1 negative 261 PCIE_WAKE PCIE_WAKE PCIE_WAKE 262 GND GND GND 263 LCD_BL_PWM1 GPIO4_C6/PWM1 Touch panel reset input I/O DOWN 264 MIPI_RX0_CLKP MIPI_RX0_CLKP MIPI-CSI0 differential clock lane positive 265 LCD_BL_PWM0 GPIO4_C2/PWM0/VOP1_PWM_CABC LCD panel backlight brightness control output I/O DOWN 266 MIPI_RX0_CLKN MIPI_RX0_CLKN MIPI-CSI0 differential clock lane negative 267 VCCA3V0_CODEC VCCA3V0_CODEC Output Voltage 3.0V 268 GND GND GND 269 VCCA3V0_CODEC VCCA3V0_CODEC Output Voltage 3.0V 270 MIPI_RX0_D2P MIPI_RX0_D2P MIPI-CSI0 differential lane 2 positive 271 VCCA1V8_CODEC VCCA1V8_CODEC Output Voltage 1.8V 272 MIPI_RX0_D2N MIPI_RX0_D2N MIPI-CSI0 differential lane 2 negative 273 VCCA1V8_CODEC VCCA1V8_CODEC Output Voltage 1.8V 274 GND GND GND 275 GND GND GND 276 MIPI_RX0_D3P MIPI_RX0_D3P MIPI-CSI0 differential lane 3 positive 277 I2S0_SCLK GPIO3_D0/I2S0_SCLK I2S 0 port, for audio codec I/O DOWN 278 MIPI_RX0_D3N MIPI_RX0_D3N MIPI-CSI0 differential lane 3 negative 279 I2S0_LRCK_RX GPIO3_D1/I2S0_LRCK_RX I2S 0 port, for audio codec I/O DOWN 280 GND GND GND 281 I2S0_LRCK_TX GPIO3_D2/I2S0_LRCK_TX I2S 0 port, for audio codec I/O DOWN 282 MIPI_TX1/RX1_D3P MIPI_TX1/RX1_D3P MIPI-DSI1/CSI1 differential lane 3 positive 283 I2S0_SDI0 GPIO3_D3/I2S0_SDI0 I2S 0 port, for audio codec I/O DOWN 284 MIPI_TX1/RX1_D3N MIPI_TX1/RX1_D3N MIPI-DSI1/CSI1 differential lane 3 negative

21 285 I2S0_SDO3 GPIO3_D4/I2S0_SDI1SDO3 I2S 0 port, for audio codec I/O DOWN 286 GND GND GND 287 I2S0_SDO2 GPIO3_D5/I2S0_SDI2SDO2 I2S 0 port, for audio codec I/O DOWN 288 MIPI_TX1/RX1_D2P MIPI_TX1/RX1_D2P MIPI-DSI1/CSI1 differential lane 2 positive 289 I2S0_SDO1 GPIO3_D6/I2S0_SDI3SDO1 I2S 0 port, for audio codec I/O DOWN 290 MIPI_TX1/RX1_D2N MIPI_TX1/RX1_D2N MIPI-DSI1/CSI1 differential lane 2 negative 291 I2S0_SDO0 GPIO3_D7/I2S0_SDO0 I2S 0 port, for audio codec I/O DOWN 292 GND GND GND 293 I2S_CLK GPIO4_A0/I2S_CLK I2S MCLK, for both I2S0 and I2S1 I/O DOWN 294 MIPI_TX1/RX1_CLKP MIPI_TX1/RX1_CLKP MIPI-DSI1/CSI1 differential clock lane positive HDMI input power enable for VCC1V8 295 I2S1_SCLK GPIO4_A3/I2S1_SCLK I2S 1 port, for BT module 296 MIPI_TX1/RX1_CLKN MIPI_TX1/RX1_CLKN MIPI-DSI1/CSI1 differential clock lane negative I/O DOWN 297 I2S1_LRCK_RX GPIO4_A4/I2S1_LRCK_RX HDMI input reset output I2S 1 port, for BT module I/O DOWN 298 GND GND GND 299 I2S1_LRCK_TX GPIO4_A5/I2S1_LRCK_TX HDMI input interrupt input I2S 1 port, for BT module I/O DOWN 300 MIPI_TX1/RX1_D1P MIPI_TX1/RX1_D1P MIPI-DSI1/CSI1 differential lane 1 positive 301 I2S1_SDI0 GPIO4_A6/I2S1_SDI0 HDMI input standby enable I2S 1 port, for BT module I/O DOWN 302 MIPI_TX1/RX1_D1N MIPI_TX1/RX1_D1N MIPI-DSI1/CSI1 differential lane 1 negative 303 I2S1_SDO0 GPIO4_A7/I2S1_SDO0 I2S 1 port, for BT module I/O DOWN 304 GND GND GND 305 GND GND GND 306 MIPI_TX1/RX1_D0P MIPI_TX1/RX1_D0P MIPI-DSI1/CSI1 differential lane 0 positive 307 I2C1_SDA GPIO4_A1/I2C1_SDA I2C serial port 1,for Audio, need external pull-up I/O UP 308 MIPI_TX1/RX1_D0N MIPI_TX1/RX1_D0N MIPI-DSI1/CSI1 differential lane 0 negative 309 I2C1_SCL GPIO4_A2/I2C1_SCL I2C serial port 1,for Audio, need external pull-up I/O UP 311 EAR_CTL GPIO4_C5/SPDIF_TX HDMI digital audio potical output I/O DOWN

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