奈 錄 奈 1-1 CMOS 奈 1-2 邏 1-3 1-4 路. 奈 金 2-1 2-2 2-3 2-4, 奈 3-1 3-2 3-3 3-4 奈 4-1 4-2 奈 料 4-3 奈 料 4-4 奈 5-1 5-2 奈 5-3 奈 量 錄 I 1
奈 1-1 CMOS 奈 了 數 度 都不 都 innovation 參數 1 奈 更 1. 諸 (after ITRS roadmap 2003) 神 數 2E10 神 連 數 100~10,000 量 1.3 kg 600cm 3 率 15-30 W 1E12 bits 料 理 度 1E10 bits/sec CMOS (complementary metal oxide silicon) 利 scaling 來 來 度 constant electrical field scaling 率 power density technology node IC 連 度 MOSFET 度 更 MOSFET 度 26mV V T constant electrical field scaling 0.2V off-state 流 2 流 I Dsat V DD constant electrical field 來 1-1 率 度 1.3 率 standby power 3 率 若 SiO 2 數 更 漏 流 率 4 1-2 率 bipolar transistor 90 年 CMOS 路 CMOS 路 率 IC 量 1-3 率 來奈 2
V/α t ox /α GATE WIRING W/α n - n + source drain L/α x d /α psubstrate, doping α*n A Voltage: V/α Oxide: t ox /α Wire width: L/α Gate Width: x d /α Substrate: α*n A RESULTS: Higher Density: ~ α 2 1000 100 10 1 classic scaling T ox (Å) V dd ( ) V t ( ) Higher Speed: ~α 0.1 Power/ckt: ~1/α 2 0.01 0.1 1 Power Density: ~ Constant Gate Length, Lgate(µm) 1-1. MOS SiO 2 度 V dd V t 度 [1], after B. S. Meyerson, 2004 度 T ox Å Leff and Vdd Active Power Density ~ 1.3X/generation Passive Power Density ~ 3X/generation Gate Leakage Power Density > 4X/generation Power (W/cm 2 ) 1E+03 1E+02 1E+01 1E+00 1E-01 1E-02 1E-03 1E-04 Standby Power Density Active Power Density 1E-05 0.01 0.1 Gate Length (µm) 1 1-2. 率 度 [1]. after B. S. Meyerson, 2004 率 路 HP high performance LOP low operation power LSTP low standby power HP 度 Pentium CPU 率 不 LOP 率 note book IC 若 量 standby power 3
不 LSTP 不 率 量 不 省 Result : CMOS power densities escalate unacceptably 14 12 Bipolar Module Heat (watts/cm 2 ) 10 8 6 4 2 CMOS 5W/cm 2 0 1950 1960 1970 1980 1990 2000 2010 1-3. bipolar CMOS 路 率 [1], after B. S. Meyerson 2004 CMOS 率 流 漏 high k dielectrics 來 oxynitride C g ε = 數 ε t 度 1-4 度 < 2nm 0.25nm 2V 漏 流 10X 度 3nm 漏 流 1E-4 A/cm 2 1-4. 漏 流 度 度 [2] 1997 IEEE 4
了 漏 HP 流 V t 0.2V 了 率 maximum osilation frequency f max 金 metal gate 來 poly gate 降 數 CMOS high k metal gate CMOS 率 更 CMOS 1-5 4 列 列 利 strain 率 mobility 利 silicon on insulato SOI 數 流 current drive memory 邏 logic 列 1-5 3 列 2 列 了 路 architecture 列 1 列 Emerging Research Devices Emerging Technology Sequence Emerging Technology Vectors 列 Cellular array Defect tolerant Biologically inspired Quantum computing Architecture 列 RSFQ Floating body DRAM Nano FG SET Insulator resistance change Molecular Logic 列 Phase change 1-D structures Resonant tunneling SET Molecular QCA Spin transistor Memory 列 Transport enhanced FETs UTB single gate FET Sourec/Drain engineered FET UTB multiple gate FET Quasi ballistic FET Nonclassical CMOS Figure 38 Emerging Technology Sequence Risk 1-5. ITRS 2003 [3], after ITRS roadmap 2003 5
1-2 邏 MOS 易 IC strained Si Intel prescott pentium chip 例 NMOS tensile stress 力 PMOS 力 compressive stress 洞 率 mobility µ 流 W I D ~ µ ( V ) α CV Cox GS Vt 度 t = HP 路 L I D strained Si SOI SSOI 1-6. SOI (after ITRS roadmap 2003) ultra thin body SOI 若 Si 度 4nm 度 4 3 12nm 22nm buried oxide BOX 列 1-6 欄 SOI Si doping 度 1-7 mobility 若 Si 度 Si BOX 度 mobility 降 6
Electron Mobility, µ eff (cm 2 /Vs) 1000 800 600 400 200 Universal Mobility 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Vertical E-field, E eff (MV/cm) Hole Mobility, µ eff (cm 2 /Vs) 200 150 100 50 Universal Mobility 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Vertical E-field, E eff (MV/cm) 1-7. 洞 率 1-8. / FET(after ITRS roadmap 2003) 7
1 MOS 流 10 利 Schottky 降 I on on state 流 1-8 I off 不 流 / 降 / / 1-8 浪 了 channel 1-9 若 4 gate 4 流 4 oxide 流 1-9. MOSFET 若 度 electro static 流 scaling MOS N-gate N 2 若 Si gate control 更 1-10. Tied gate 連 (after ITRS roadmap 2003) 8
Independently switched gates, planar conduction LOP and LSTP CMOS Vertical conduction HP, LOP, and LSTP CMOS 1-11. 立 (after ITRS roadmap 2003) FET 離 若 連 tied double gate FET 若 不 independent switch gate 流 行 1-11 行 度 度 sidewall conduction 1-10 度 行 planar conduction 1-10 ITRS international technology roadmap of semiconductor CMOS SOI high k metal gate 16nm MOS 度 7nm 度 7nm 2019 年 CMOS 度 2 MOSFET 邏 1. Rapid Single Flux Quantum RSFQ Josephson 量 量 量 1 flux quanta 0 flux 0 1 狀 量 0.3µm 度 250GHz 度 度 77K 利 High Tc super conductor HTS 度 2. 1D carbon nanotube Si wire 1D 1D bulk 9
2. 邏 (after ITRS roadmap 2003) Availability Sequence 1 2 2-3 2-3 4 5 6 Device FET RSFQ [A,B,C] 1D structures Resonant Tunneling Devices Types Si CMOS JJ CNT FET RTD-FET Supported Architectures Cell Size (spatial pitch) Density (devices/cm 2 ) NW FET NW heterostructures Crossbar nanostructure Conventional Pulse Conventional Cross-bar RTT Conventional CNN SET CNN SET Molecular QCA (E) Spin transistor 2-terminal 3-terminal FET 3-terminal bipolar transistor NEMS Molecular QCA Memorybased QCA E:QCA M:QCA QCA Spin FET (SFET) Spin-valve transistor (SVT) Quantum Programmable logic 100 nm 0.3 µm 100 nm 100 nm 40 nm Not known 60 nm 100 nm 3E9 1E6 3E9 3E9 6E10 1E12 3E10 3E9 Switch Speed 700 GHz 1.2 THz Not known 1 THz 1 GHz Not Known 30 MHz 700 GHz Circuit Speed Switching Energy, J Binary 30 GHz 250-800 GHz 30 GHz 30 GHz 1 GHz 2 10-18 2 10-19 Nb [>1.4 10-17 ] < 1 MHz (NEMS) 1 10-18 1.3 10-16 2 10-18 > 2 10-18 [>1.5 10-17 ] [C] (NEMS) 1 MHz 30 GHz [E:>1 10-18 ] [E] 2 10-18 M:>4 10-17 Throughput GBit/ns/cm 2 86 0.4 86 86 10 N/A 0.06 86 Gain Must be>>1 for all devices, See Table 63b for experimental values Operational Temperature RT 4K(Nb) 77K(HTS) 20K(M g B 2 ) RT RT 20 K RT E:QCA Cryogenic M:QCART CD Tolerance Critical Not critical Not critical Very critical Very critical Not critical Very critical <2%(M:QCA) Materials System Si Nb HTS Mart Complex Circuit Demonstrated CNT Si - - Si-Ge See Table 63b - Si C-60 Al/Al 2 O 3 (E: QCA) Cryogenic (SFET) RT (SVT) Critical - (SFET) Si/FM(SVT) 料 1 率 2 數 coherent 10
3. Resonant tunneling 流 - 流 barrier 度 數 數 不易 度 1THz 4. single electron transistor SET MOSFET / 來 pn 量 度 量 若 2 nm 度 20K 度 1GHz 度 10 11 cm -2 流 數 路 fan out 不 率 5. molecule 利 連 利 overlap 流 降 流 利 例 金 filament 益 6. Quantum cellular automata QCA 利 local interconnect 流 力不 列 不 流 利 力 E QCA 力 M QCA 例 利 4 量 4 落 1-12 狀 AD BC 量 量 離 量 20nm 60nm 利 邏 路 QCA 更 celluar non-linear network CNN inverter 7 QCA QCA 度 利 THz MHz 度 7K A B C D 1-12. 4 量 7. 利 spin-fet spin-valve spin-fet 利 FET ferromagnetic 料 spin-polarized spinvalve 11
BJT 都 ferromagnetic nonmagnetic 料 gain spinfet 3. (after ITRS roadmap 2003) Present Day Baseline Technologies Phase Change Memory Floating Body DRAM Nano-floating Gate Memory Single/Few Electron Memories Insulator Resistance Change Memory Molecular Memories Storage Mechanism Engineered Device Bi-stable DRAM NOR Flash OUM ITDRAM Tunnel barrier SET MIM Types switch Or nanocrystal Availability 2004 2004 ~2006 ~2006 >2006 >2007 ~2010 >2010 Cell Elements 1T1C 1T 1T1R 1T 1T 1T 1T1R 1T1R Initial F 90 nm 90 nm 100 nm 70 nm 80 nm 65 nm 65 nm 45 nm Cell Size 8F 2 12.5F 2 ~6F 2 ~4F 2[A] ~6F 2 ~6F 2 ~6F 2 0.065 µm 2 0.101 µm 2 0.06 µm 2 0.0049 µm 2 0.038 µm 2 0.025 µm 2 0.025 µm 2 Not known Access Time < 15 ns ~ 80 ns <100 ns <10 ns [A,C] <10 ns <10 ns Slow ~10 ns Store Time < 15 ns ~ 1 ms <100 ns <10 ns [A,C] <10 ns <100 ns <100 ns ~10 ns Retention Time 64 ms 10-20 yrs >10 yrs <10 ms [A] >10 yrs ~100 sec ~1 year ~1 month E/W Cycles Infinite 1E5 >1E13 >1E15 [A] >1E6 >1E9 >1E3 >1E15 General Advantages Challenges Density Economy Non-volatile Multi-bit cell Non-volatile Low power Rad hard Multi-bit cells Density Economy Non-volatile Density Fast read and Low power write Multi-bit cells Scaling Scaling Large E/W Need SOI Material quality current Retention versus New scaling Materials Dopant and integration fluctuation Endurance Low voltage Multi-bit cells Density Low power 3D potential Defect tolerant Dimension New Volatile control for RT operation materials and Thermal stability integration Slow access Background Speed versus charge R trade-off disturb Maturity Production Production Development Demonstrated Research Research Research Research Research Activity 3 3 61 40 3 43 12
1-3 利 CMOS platform 例 4 FET SRAM static random access memory 1 1 1T1C DRAM 3 行 cell element DRAM dynamic Random access memory Flash 列 1 2 欄 1. PCM phase change memory OUM ovonic unified memory 利 流 chalcogenide vs 不 cell elements ITIR 1 1 2. 利 SOI partially depleted MOSFET floating body floating body DRAM cell 3. floating gate MOSFET nanofloating gate memory NFGM 1 / 洞 2 gate 奈 4. 利 量 1 數 來 conductance 量 5. Insulator Resistance change Memory 利 金 - - 金 MIM 見 SrZrO 3 Ba Sr TiO 3 MIM 不 讀 不 不 狀 RC 度 6. 利 連 不 度不 識 來 1-4 路 奈 MOSFET 不 MOSFET 路 路 不 奈 路 1. Parallel cellular Array 行 列 1 QCA 利 來 2 CNN Cellular Nonlinear Network 數 來 狀 數 連 數 利 狀 數 數 VLSI 易 2. Defect tolerant architecture 奈 度 利 redundant 奈 路 不良 路 3. bio inspired architecture 利 類 路 13
類 利 量 連 1000 10000 連 行 理 奈 4. 量 (coherent quantum computing), 量 利 數 理 qubit qubit 利 qubit 利 數 行 行 度 讀 料 數 讀 數 14
參 1. B. Meyerson IBM Innovation the future si technology 90nm and beyond Taipei Taiwan Jan 2004 2. Y. Taur IEEE spectrum July 1999 3. Semiconductor Industry Association. The International Technology Roadmap for Semiconductors, 2003 edition. International SEMATECH:Austin, TX, 2003. 15