2 奈米線之製備與相關元件之研製與分析 Preparation and Device Fabrication of Si Nanowires 計畫編號 :NSC E 執行期間 :94 年 8 月 1 日至 95 年 7 月 31 日主持人 : 林鴻志交通大學電子工程系副教授 一 摘要中文摘要本專題計畫提出一種成本不高 製程步驟簡易的新穎矽奈米線之製備方式, 目的為改善一般由 top-down 製造矽奈米線的主要缺點 : 製程設備昂貴或流程複雜 此方法主要是在矽晶圓上沉積薄絕緣層, 利用 I-line stepper 微影和化學濕蝕刻方式將此絕緣層微縮至奈米級大小 以此微影蝕刻後之絕緣層當作硬遮蔽層 (hard mask), 再乾蝕刻矽基板, 便可使形成奈米線結構 此製備方式除了製程簡單和低成本之優點外, 其所形成之奈米線的直徑 長度和晶格座向更可精確地控制 此外, 經由穿透式顯微鏡 (TEM) 之分析, 可證實所製備出來之矽奈米線擁有良好之結晶特性 因此, 相信本製造方法可提供再現性高和可靠度佳之矽奈米線, 以應用至相關之元件產品 英文摘要 In this project, a novel approach for preparation of silicon naonwires (SiNWs) via straightforward and economic process is proposed and demonstrated. This technique utilizes non-critical photolithography and etching steps to define the NWs with good control over the structural parameters such as the orientation, diameter and length. It is superior to conventional top-down manners in terms of lower cost and simplified process flow. In this process, I-line photolithography is used to define the original diameter of hard mask patterns to a sub-micrometer feature size. By using chemical wet etching, the size of hard mask is further shrunk to sub-100 nm. With this nano-scale hard mask, SiNWs can be acquired after an anisotropic dry etching of Si substrate, albeit no expensive lithography tool is involved in the process flow. 二 計畫的緣由與目的矽奈米線結構近來已受到各個研究團隊的矚目 藉由其高表面積 / 體積比, 奈米結構表面的狀況將會對奈米線內部的載子傳導有深切的影響 利用此性質, 奈米線對於感測元件應用可提供相當高的偵測靈敏度  一般製備奈米線的方式主要分為兩類, 一是 bottom-up , 另一為 top-down  在大部份 bottom-up 的方式中, 以金屬催化成長來形成奈米線是最為常見的 此法可用來製備不同材料的奈米線, 除了矽奈米線外, 還有鍺 (Ge) 奈米線  磷化銦(InP) 奈米線  等 因此這個方式為各個相關研究機構主要的研究方法 但是金屬催化成長目前仍有一些問題存在, 如奈米線的長度 直徑和晶格座向皆無法受到良好的控制, 以及在晶圓上無法準確地定位, 這意味其有著再現性不高的疑慮 同時, 金屬奈米粒子的使用亦是一個潛在污染的議題 所以, 這些問題的存在, 將會限制一要求高性能表現之奈米線電子元件的製作 一般以 top-down 製作奈米線的方法, 如使用 deep UV  和 e-beam  等曝光設備, 或許可以解決這些課 2
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6 附件 A Novel Method for the Preparation of Si Nanowires Raymond Lin 1, Horng-Chih Lin 1, 2, *, Jung-Yen Yang 1, Shih-Wen Shen 1, and Chun-Jung Su 2 1 National Nano Device Laboratories 2 Department of Electronics Engineering and Institute of Electronics Engineering, National Chiao Tung University 1001 Ta-Hsueh Road, Hsinchu, Taiwan 300, ROC *Phone: ext:54193, Fax: , 1. Introduction Si nanowire (SiNW) structures have recently attracted a lot of attentions. By taking advantage of the high surface-to-volume ratio inherent in the structure, NWs can provide high surface sensitivity for sensing device applications , . The preparation methods of NWs could be categorized into two types, namely, top-down and bottom-up . Among a number of bottom-up approaches, catalytic growth is probably the most popular. This method is suitable for preparing various kinds of NW materials and can even be applied for forming NW heterostructures . It is thus very flexible and suitable for the feasibility study in laboratories. However, there also exist some issues, such as the difficulty in controlling the NW dimensions including length and diameter, as well as the NW orientation . Moreover, the use of metal nano particles as the catalyst represents a potential contamination issue. These issues may hinder practical applications. Besides, the manufacturing of NW devices may suffer from the uncontrollability of structural parameters such as NW s length and diameter. Thus the precise positioning of the NWs represents another major obstacle for reliable device fabrication. These issues probably could be overcome by using the top-down approaches that usually rely on advanced lithography tools, like the DUV steppers and e-beam lithography technique , to form the NW structures. Nevertheless, the process cost could be high owing to the use of costly lithography tools. In this work we proposed and demonstrated a simple and promising approach that could effectively address the above issues. This approach belongs to the top-down category albeit no costly lithography step is involved. 2. Preparation and Characterization of SiNWs Detailed process sequence is illustrated in Fig. 1. Firstly, the starting Si wafers were oxidized, then a g-line stepper was used to form periodic PR patterns on the surface. The PR patterns were transferred to the underlying oxide layer by a plasma etch step. Oxide trimming was subsequently performed in an HF solution to further shrink the dimension of the oxide structure. This step allows us to scale the patterns into nano-scale dimension without resorting to expensive equipments. With careful tuning of the etching conditions, the precise control over the structural dimensions is feasible. After the oxide trimming, the PR patterns were stripped off, followed by a Si etch step performed in a high-density plasma etcher with the remaining oxide structures as the hardmask. Figure 2 shows several Si pillar structures having a height of around 2 µm. Figure 2(a) shows a sample that did not receive the oxide trimming treatment and the diameter is 1.3 µm. Figure 2(b)~(d) are the formed NW structures with diameter of 40, 30, and <30 nm, respectively. Note that the structure becomes very flexible when scaled below 30 nm. Using the above samples, we ve also developed a method to prepare a solution that contains Si NWs, as shown in Fig. 3. Wafers were then immersed in the solution and treated with megasonic oscillation to break the NWs from their root. Afterwards, wafers were removed and the solution was harvested. The solution could then be used as a source for forming aligned Si NWs on many kinds of substrates for electronic applications , . Figure 4 shows the TEM image and the corresponding diffraction pattern of a SiNW structure. It is seen that good crystallinity could be retained. 3. Conclusion In conclusion, we have proposed and demonstrated a very simple and low-cost method to fabricate silicon nano wires without resorting to expensive tools or complex processes. Besides, the processed wafers could be recycled and reused after suitable treatment. In contrast to the conventional approach using metal catalytic growth, the new method is essentially metal free and provides good control over the NW length, diameter, and orientation. Acknowledgments The authors would like to thank the staff at National Nano Device Laboratories (NDL) for assistance in device fabrication. This work was supported in part by the National Science Council of the Republic of China under contract number NSC E
7 References:  Y. Cui et al, Science Vol. 293, pp (2001).  J. Hanm et al, Nano Lett., Vol. 4, pp (2004).  A. M. Morales et al, Science, Vol. 279, pp (1998).  X. Duan et al, Adv. Mat., Vol.12, pp.298 (2000).  M. S. Gudiksen et al, J. Phys. Chem. B, Vol. 105, pp (1998).  Horng-Chih Lin et al, IEEE Electron Device Letters Vol.24, pp (2003).  X. Duan et al, Nature, Vol. 425, pp (2003).  M. C. McAlpine et al, Nano Lett., Vol. 3, pp (2003). Fig.1 Process flow for the preparation of SiNWs. (a) (c) (b) (d) Fig.2 SEM pictures of the patterned Si pillar structures with diameter (a) 1.3 µm, (b) 40 nm, (c) 30 nm, and (d) <30 nm. Fig.3 Preparation of NW solution. Fig.4 TEM image of the SiNW.