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1 PPC82

2 V

3 WINDOWS REDHAT LINUX LINUX uimgae ramdisk uboot Linux MTD MPC GPIO LED FCC1 FCC2 FCC

4 PPC82 MPC82 PPC82 PowerPC PCI PPC82 PPC82 128M SDRAM 8M FLASH NAND FLASH 10M/100M RS-232 (COM1) Linux PPC82 PPC82 PPC82 LINUX PPC82 PPC8260/8270/8280 PPC e core with 16K inst and 16K data caches 64-bit 60x bus 32-bit PCI bus 128K ROM 32K IRAM 32K DPRAM Three FCCs for 10/100 Ethernet 128 HDLC channels 4 TDMs 4 SCCs 2 SMCs SPI I2C Memory controller built from SDRAM UPM GPCM machines New features -- USB RMII Performance 333 MHz CPU 250 MHz CPM 83 MHz bus 450 MHz CPU 300 MHz CPM 100 MHz bus Less than full performance 1.5V Technology HIP7AP 3.3V I/O 1.5V Core 480 TBGA 37.5x37.5mm 1.27mm ball pitch PPC82xx + ATX 4

5 CPU MPC8270 SDRAM K4S x4(128mbyte) BOOT FLASH AM29LV640(8MByte) Nand FLASH K9F FLASH CPU JTAG SMC1 SMC2 SCC1 3 SMC1 3 FCC1 FCC2 FCC V 5V/3A ATX BOOTLOADER U-BOOT Motavista Linux DENX Linux mm x 86mm 178mm x 134mm MPC8270 MPC8270 DB9 5V/3A 1 5

6 6

7 4 PCB RedHat Linux90 3 bootloader for MPC8270 linux Linux pdf ProtelDXP2004 PCB pdf ProtelDXP2004 PCB PCB 1 WINDOWS PC 1 > > > COM V uboot Linux

8 1.1 WINDOWS MPC8250 8

9 PC 1 LINUX 9

10 login eth0 status root ls LINUX ifconfig ppc82 eth0 FCC0 eth1 FCC1 eth2 FCC2 ifconfig eth IPADDR ifconfig eth ifconfig eth

11 ifconfig eth PC IP PC IP IP IP ping eth1 IP PC IP ping ping telnet PC 11

12 2.2 REDHAT LINUX PC REDHAT LINUX CDROM mount /dev/cdrom /mnt/cdrom cd /mnt/cdrom CDROM./inst y LINUX uimgae ramdisk LINUX uimage cd /PPC8270/usr/src/linux make uimage make dep LINUX uimage /tftpbootboot date ls uimage date ls -la /tftpbootboot/uimage ramdisk /PPC8270/usr/src/ramdisk/ramdisk.image.gz cd /PPC8270/usr/src/ramdisk tar zxf ramdisk.image.gz ramdisk.image mount test mkdir test( test ) mount o loop ramdisk.image test test bin hello bin cp /PPC8270/usr/src/application/hello/hello /PPC8270/usr/src/ramdisk/test/bin test umount umount test./image.sh ramdisk.img /tftpbootboot /tftpbootboot ramdisk.img uimage ramdisk uboot sdram ram 12

13 flash tftpboot tftpboot minicom ( N1 ) minicom uboot uboot uboot flash Linux 3 uboot tftpboot uimage /tftpboot/uimage tftpboot a00000 ramdisk.img /tftpboot/ramdisk.img a00000 flash ram Linux bootm a00000 ( ) flash tftpboot uimage erase 0xfff xffffffff cp.b 0x xfff SIZE tftpboot a00000 uimage erase 0xff xffcfffff cp.b 0x xff SIZE SIZE uboot tftpboot printenv/setenv/saveenv uboot doc DENX PPCBoot and Linux Guide 13

14 PPC82 MOTOROLA PPC8270 RS232 LINUX REDHAT LINUX PC PPC8270 FLASH PC FLASH PC PPC8270 PPC8270 PC CPU Vxwork psos Neculeus Windows CE LINUX Linux Linux Internet 14

15 linux Linux Linux Linux TCP/IP Linux Linux Linux Linux UNIX LINUX LINUX PC linux forpowerpc lists.ppc8270.org Linux native HOST PC 15

16 1 NFS 2 JTAG JTAG JTAG Abatron BDI2000 FLASH INTEL PPC8270 MOTOROLA PowerPC 8270 GNU PC LINUX REDHAT LINUX REDHAT 9.0 PC NFS mount FTP TFTP RedHat9.0 l PC LINUX RedHat9.0 Custom Package everything Linux Linux Linux No firewall 2 TFTP FTP Enable Running RTL8139 REDHAT9.0 IP ifconfig eth TFTP RedHat9.0 /etc/xinetd.d/tftp disable no 16

17 service tftp { socket_type = dgram protocol = udp wait = yes user = root server = /usr/sbin/in.tftpd server_args = -s/tftpboot disable = no per_source = 11 cps = 1002 flags = IPv4 } /etc/xinetd.d/telnet /etc/xinetd.d/rsh setup [system service] tftp xinetd /etc/init.d/xinet.d restart service xinet.d restart tftpboot FTP RedHat9.0 /etc/vsftpd.ftpusers /etc/vsftpd.user_list nobody /etc/vsftpd.ftpusers # Users that are not allowed to login via ftp root bin daemon adm lp sync shutdown halt mail news uucp operator games root service vsftpd restart CDROM mount /dev/cdrom /mnt /dev/cdrom CDROM /dev/hdb mount t iso9660 /dev/hdb /mnt 17

18 cd /mnt mount./inst y y /PPC8270 /PPC8270/usr/src/ramdisk ramdisk /PPC8270/usr/src/application/ /PPC8270/usr/src/tarballs/ LINUX /PPC8270/usr/src/ linux _mvl31 LINUX /opt/ LINUX /PPC8270/usr/src/ u-boot uboot PPC8270 root@(none):/# ls bin dev home lost+found myapp proc sbin usr boot etc lib mnt opt root tmp var /PPC8270/usr/src/ramdisk root.ext2 /bin/ /dev/ uboot 3 Linux Linux uboot Linux ppc_82xx-gcc -o hello_world hello_world.c file hello_world hello_world: ELF 32-bit MSB executable, PowerPC or cisco 4500, version 1 (SYSV),for GNU/Linux 2.2.5, dynamically linked (uses shared libs), not stripped PowerPC linux PPC82 JTAG JTAG Abatron BDI2000 FLASH BDI cfg bdigdb Configuration File For NPW755 (MPC755 + MPC8250) System Shen Rong <rshen@udtech.com.cn> [INIT] init core register WREG MSR 0x MSR -- ME, RI,FP WREG MSR 0x MSR -- FP, RI 18

19 Chip select FLASH (16bit 8MB) WM32 0x xFF BR0 WM32 0x xFF800Cf6 OR0 WM32 0x xFFFFFF03 SYPCR WM32 0x x BCR WM32 0x x4224C000 SIUMCR WM16 0x E 0x556C SWSR WM16 0x E 0xAA39 SWSR >> should be confirmed WM32 0x000101a8 0xF change immr WM32 0xF x BR2 WM32 0xF xF8002AC0 OR2 SDRAM init(sdram machine) WM16 0xF x2000 MPTPR WM8 0xF001019C 0x32 PSRT WM32 0xF x832DA46E PSDMR1 -- normal opt, disable refresh WM32 0xF xAB2DA46E PSDMR2 -- precharge WM8 0x xFF MEM1 -- a write following the precharge WM32 0xF x8B2DA46E PSDMR3 -- CBR refresh WM8 0x xFF MEM2 WM8 0x xFF MEM3 WM8 0x xFF MEM4 WM8 0x xFF MEM5 WM8 0x xFF MEM6 WM8 0x xFF MEM7 WM8 0x xFF MEM8 WM8 0x xFF MEM9 WM32 0xF x9B2DA46E PSDMR4 -- mode register write WM8 0x xFF MEM10 -- mode value WM32 0xF xDB2DA46E PSDMR5 -- enable auto refresh WM32 0xF xC32DA46E PSDMR6 -- normal opt, auto refresh enabled SDRAM init end 19

20 WM32 0x0 0x WM32 0x4 0x [TARGET] CPUTYPE 8260 the CPU type (603EV,750,8240,8260) JTAGCLOCK 0 use 16 MHz JTAG clock WORKSPACE 0x workspace for fast download and cache flush BDIMODE AGENT the BDI working mode (LOADONLY AGENT GATEWAY) BREAKMODE SOFT SOFT or HARD, HARD uses PPC hardware breakpoint MMU XLAT translate effective to physical address PTBASE 0x000000f0 here is the pointer to the page table pointers DCACHE FLUSH VECTOR CATCH catch unhandled exceptions MEMDELAY 2000 additional memory access delay PARITY ON enable data parity generation POWERUP 200 WAKEUP 200 [HOST] IP FILE E:\bdi2000\powerpc\ppcboot.bin FORMAT BIN LOAD MANUAL load code MANUAL or AUTO after reset DEBUGPORT 2001 [FLASH] CHIPTYPE AM29BX16 Flash type AMD29LV640 CHIPSIZE 0x The size of one flash chip in bytes: 8M(e.g. AM29F010 = 0x20000) BUSWIDTH 16 The width of the flash memory bus in bits ( ) FILE 8250_head.bin FORMAT BIN 0xFFE00000 ERASE 0XFE BLOCK ERASE 0XFFE00000 BLOCK WORKSPACE 0x workspace in target RAM for fast download [REGS] DMM1 FILE 0x reg8260.def 20

21 reg8260.def PPC82 Register definition for MPC8260 =============================== name: user defined name of the register type: the type of the register GPR general purpose register SPR special purpose register MM memory mapped register DMMx direct memory mapped register with offset x = 1..4 the base is defined in the configuration file e.g. DMM1 0x addr: the number, adddress or offset of the register size the size of the register (8,16 or 32) name type addr size sp GPR 1 xer SPR 1 lr SPR 8 ctr SPR 9 dsisr SPR 18 dar SPR 19 dec SPR 22 sdr1 SPR 25 srr0 SPR 26 srr1 SPR 27 tbl SPR 268 tbu SPR 269 sprg0 SPR 272 sprg1 SPR 273 sprg2 SPR 274 sprg3 SPR 275 ear SPR 282 pvr SPR 287 ibat0u SPR 528 ibat0l SPR 529 ibat1u SPR 530 ibat1l SPR

22 ibat2u SPR 532 ibat2l SPR 533 ibat3u SPR 534 ibat3l SPR 535 dbat0u SPR 536 dbat0l SPR 537 dbat1u SPR 538 dbat1l SPR 539 dbat2u SPR 540 dbat2l SPR 541 dbat3u SPR 542 dbat3l SPR 543 dmiss SPR 976 dcmp SPR 977 imiss SPR 980 icmp SPR 981 rpa SPR 982 hid0 SPR 1008 hid1 SPR 1009 hid2 SPR 1011 DMM1 must be set to the internal memory base address General SIU siumcr DMM1 0x sypcr DMM1 0x swsr DMM1 0x1000e 16 bcr DMM1 0x ppc_acr DMM1 0x ppc_alrh DMM1 0x1002c 32 ppc_alrl DMM1 0x lcl_acr DMM1 0x lcl_alrh DMM1 0x lcl_alrl DMM1 0x1003c 32 tescr1 DMM1 0x l_tescr1 DMM1 0x l_tescr2 DMM1 0x1004c 32 pdtea DMM1 0x pdtem DMM1 0x10054 bdigdb Configuration File For NPW755 (MPC755 + MPC8250) System 22

23 Shen Rong [INIT] init core register WREG MSR 0x MSR -- ME, RI,FP WREG MSR 0x MSR -- FP, RI Chip select FLASH (16bit 8MB) WM32 0x xFF BR0 WM32 0x xFF800Cf6 OR0 WM32 0x xFFFFFF03 SYPCR WM32 0x x BCR WM32 0x x4224C000 SIUMCR WM16 0x E 0x556C SWSR WM16 0x E 0xAA39 SWSR >> should be confirmed WM32 0x000101a8 0xF change immr WM32 0xF x BR2 WM32 0xF xF8002AC0 OR2 SDRAM init(sdram machine) WM16 0xF x2000 MPTPR WM8 0xF001019C 0x32 PSRT WM32 0xF x832DA46E PSDMR1 -- normal opt, disable refresh WM32 0xF xAB2DA46E PSDMR2 -- precharge WM8 0x xFF MEM1 -- a write following the precharge WM32 0xF x8B2DA46E PSDMR3 -- CBR refresh WM8 0x xFF MEM2 WM8 0x xFF MEM3 WM8 0x xFF MEM4 WM8 0x xFF MEM5 WM8 0x xFF MEM6 WM8 0x xFF MEM7 23

24 WM8 0x xFF MEM8 WM8 0x xFF MEM9 WM32 0xF x9B2DA46E PSDMR4 -- mode register write WM8 0x xFF MEM10 -- mode value WM32 0xF xDB2DA46E PSDMR5 -- enable auto refresh WM32 0xF xC32DA46E PSDMR6 -- normal opt, auto refresh enabled SDRAM init end WM32 0x0 0x WM32 0x4 0x [TARGET] CPUTYPE 8260 the CPU type (603EV,750,8240,8260) JTAGCLOCK 0 use 16 MHz JTAG clock WORKSPACE 0x workspace for fast download and cache flush BDIMODE AGENT the BDI working mode (LOADONLY AGENT GATEWAY) BREAKMODE SOFT SOFT or HARD, HARD uses PPC hardware breakpoint MMU XLAT translate effective to physical address PTBASE 0x000000f0 here is the pointer to the page table pointers DCACHE FLUSH VECTOR CATCH catch unhandled exceptions MEMDELAY 2000 additional memory access delay PARITY ON enable data parity generation POWERUP 200 WAKEUP 200 [HOST] IP FILE E:\bdi2000\powerpc\ppcboot.bin FORMAT BIN LOAD MANUAL load code MANUAL or AUTO after reset DEBUGPORT 2001 [FLASH] CHIPTYPE AM29BX16 Flash type AMD29LV640 CHIPSIZE 0x The size of one flash chip in bytes: 8M(e.g. AM29F010 = 0x20000) BUSWIDTH 16 The width of the flash memory bus in bits ( ) 24

25 FILE 8250_head.bin FORMAT BIN 0xFFE00000 ERASE 0XFE BLOCK ERASE 0XFFE00000 BLOCK WORKSPACE 0x workspace in target RAM for fast download [REGS] DMM1 0x FILE reg8260.def8 ldtea DMM1 0x ldtem DMM1 0x1005c 8 Memory Controller br0 DMM1 0x or0 DMM1 0x br1 DMM1 0x or1 DMM1 0x1010c 32 br2 DMM1 0x or2 DMM1 0x br3 DMM1 0x or3 DMM1 0x1011c 32 br4 DMM1 0x or4 DMM1 0x br5 DMM1 0x or5 DMM1 0x1012c 32 br6 DMM1 0x or6 DMM1 0x br7 DMM1 0x or7 DMM1 0x1013c 32 br8 DMM1 0x or8 DMM1 0x br9 DMM1 0x or9 DMM1 0x1014c 32 br10 DMM1 0x or10 DMM1 0x br11 DMM1 0x or11 DMM1 0x1015c 32 mar DMM1 0x mamr DMM1 0x mbmr DMM1 0x mcmr DMM1 0x mptpr DMM1 0x mdr DMM1 0x

26 psdmr DMM1 0x lsdmr DMM1 0x10194 bdigdb Configuration File For NPW755 (MPC755 + MPC8250) System Shen Rong <rshen@udtech.com.cn> [INIT] init core register WREG MSR 0x MSR -- ME, RI,FP WREG MSR 0x MSR -- FP, RI Chip select FLASH (16bit 8MB) WM32 0x xFF BR0 WM32 0x xFF800Cf6 OR0 WM32 0x xFFFFFF03 SYPCR WM32 0x x BCR WM32 0x x4224C000 SIUMCR WM16 0x E 0x556C SWSR WM16 0x E 0xAA39 SWSR >> should be confirmed WM32 0x000101a8 0xF change immr WM32 0xF x BR2 WM32 0xF xF8002AC0 OR2 SDRAM init(sdram machine) WM16 0xF x2000 MPTPR WM8 0xF001019C 0x32 PSRT WM32 0xF x832DA46E PSDMR1 -- normal opt, disable refresh WM32 0xF xAB2DA46E PSDMR2 -- precharge WM8 0x xFF MEM1 -- a write following the precharge WM32 0xF x8B2DA46E PSDMR3 -- CBR refresh WM8 0x xFF MEM2 WM8 0x xFF MEM3 WM8 0x xFF MEM4 26

27 WM8 0x xFF MEM5 WM8 0x xFF MEM6 WM8 0x xFF MEM7 WM8 0x xFF MEM8 WM8 0x xFF MEM9 WM32 0xF x9B2DA46E PSDMR4 -- mode register write WM8 0x xFF MEM10 -- mode value WM32 0xF xDB2DA46E PSDMR5 -- enable auto refresh WM32 0xF xC32DA46E PSDMR6 -- normal opt, auto refresh enabled SDRAM init end WM32 0x0 0x WM32 0x4 0x [TARGET] CPUTYPE 8260 the CPU type (603EV,750,8240,8260) JTAGCLOCK 0 use 16 MHz JTAG clock WORKSPACE 0x workspace for fast download and cache flush BDIMODE AGENT the BDI working mode (LOADONLY AGENT GATEWAY) BREAKMODE SOFT SOFT or HARD, HARD uses PPC hardware breakpoint MMU XLAT translate effective to physical address PTBASE 0x000000f0 here is the pointer to the page table pointers DCACHE FLUSH VECTOR CATCH catch unhandled exceptions MEMDELAY 2000 additional memory access delay PARITY ON enable data parity generation POWERUP 200 WAKEUP 200 [HOST] IP FILE E:\bdi2000\powerpc\ppcboot.bin FORMAT BIN LOAD MANUAL load code MANUAL or AUTO after reset DEBUGPORT 2001 [FLASH] 27

28 CHIPTYPE AM29BX16 Flash type AMD29LV640 CHIPSIZE 0x The size of one flash chip in bytes: 8M(e.g. AM29F010 = 0x20000) BUSWIDTH 16 The width of the flash memory bus in bits ( ) FILE 8250_head.bin FORMAT BIN 0xFFE00000 ERASE 0XFE BLOCK ERASE 0XFFE00000 BLOCK WORKSPACE 0x workspace in target RAM for fast download [REGS] DMM1 0x FILE reg8260.def 32 purt DMM1 0x psrt DMM1 0x1019c 8 lurt DMM1 0x101a0 8 lsrt DMM1 0x101a4 8 immr DMM1 0x101a8 32 System Integration Timers tmcntsc DMM1 0x tmcnt DMM1 0x tmcntal DMM1 0x1022c 32 piscr DMM1 0x pitc DMM1 0x pitr DMM1 0x Interrupt Controller sicr DMM1 0x10c00 16 sivec DMM1 0x10c04 32 sipnr_h DMM1 0x10c08 32 sipnr_l DMM1 0x10c0c 32 siprr DMM1 0x10c10 32 scprr_h DMM1 0x10c14 32 scprr_l DMM1 0x10c18 32 simr_h DMM1 0x10c1c 32 simr_l DMM1 0x10c20 32 siexr DMM1 0x10c24 32 Clocks and Reset sccr DMM1 0x10c80 32 scmr DMM1 0x10c88 32 rsr DMM1 0x10c90 32 rmr DMM1 0x10c

29 Input/Output Port pdira DMM1 0x10d00 32 ppara DMM1 0x10d04 32 psora DMM1 0x10d08 32 podra DMM1 0x10d0c 32 pdata DMM1 0x10d10 32 pdirb DMM1 0x10d20 32 pparb DMM1 0x10d24 32 psorb DMM1 0x10d28 32 podrb DMM1 0x10d2c 32 pdatb DMM1 0x10d30 32 pdirc DMM1 0x10d40 32 pparc DMM1 0x10d44 32 psorc DMM1 0x10d48 bdigdb Configuration File For NPW755 (MPC755 + MPC8250) System Shen Rong <rshen@udtech.com.cn> [INIT] init core register WREG MSR 0x MSR -- ME, RI,FP WREG MSR 0x MSR -- FP, RI Chip select FLASH (16bit 8MB) WM32 0x xFF BR0 WM32 0x xFF800Cf6 OR0 WM32 0x xFFFFFF03 SYPCR WM32 0x x BCR WM32 0x x4224C000 SIUMCR WM16 0x E 0x556C SWSR WM16 0x E 0xAA39 SWSR >> should be confirmed WM32 0x000101a8 0xF change immr WM32 0xF x BR2 WM32 0xF xF8002AC0 OR2 29

30 SDRAM init(sdram machine) WM16 0xF x2000 MPTPR WM8 0xF001019C 0x32 PSRT WM32 0xF x832DA46E PSDMR1 -- normal opt, disable refresh WM32 0xF xAB2DA46E PSDMR2 -- precharge WM8 0x xFF MEM1 -- a write following the precharge WM32 0xF x8B2DA46E PSDMR3 -- CBR refresh WM8 0x xFF MEM2 WM8 0x xFF MEM3 WM8 0x xFF MEM4 WM8 0x xFF MEM5 WM8 0x xFF MEM6 WM8 0x xFF MEM7 WM8 0x xFF MEM8 WM8 0x xFF MEM9 WM32 0xF x9B2DA46E PSDMR4 -- mode register write WM8 0x xFF MEM10 -- mode value WM32 0xF xDB2DA46E PSDMR5 -- enable auto refresh WM32 0xF xC32DA46E PSDMR6 -- normal opt, auto refresh enabled SDRAM init end WM32 0x0 0x WM32 0x4 0x [TARGET] CPUTYPE 8260 the CPU type (603EV,750,8240,8260) JTAGCLOCK 0 use 16 MHz JTAG clock WORKSPACE 0x workspace for fast download and cache flush BDIMODE AGENT the BDI working mode (LOADONLY AGENT GATEWAY) BREAKMODE SOFT SOFT or HARD, HARD uses PPC hardware breakpoint MMU XLAT translate effective to physical address PTBASE 0x000000f0 here is the pointer to the page table pointers DCACHE FLUSH VECTOR CATCH catch unhandled exceptions MEMDELAY 2000 additional memory access delay PARITY ON enable data parity generation 30

31 POWERUP 200 WAKEUP 200 [HOST] IP FILE E:\bdi2000\powerpc\ppcboot.bin FORMAT BIN LOAD MANUAL load code MANUAL or AUTO after reset DEBUGPORT 2001 [FLASH] CHIPTYPE AM29BX16 Flash type AMD29LV640 CHIPSIZE 0x The size of one flash chip in bytes: 8M(e.g. AM29F010 = 0x20000) BUSWIDTH 16 The width of the flash memory bus in bits ( ) FILE 8250_head.bin FORMAT BIN 0xFFE00000 ERASE 0XFE BLOCK ERASE 0XFFE00000 BLOCK WORKSPACE 0x workspace in target RAM for fast download [REGS] DMM1 0x FILE reg8260.def 32 podrc DMM1 0x10d4c 32 pdatc DMM1 0x10d50 32 pdird DMM1 0x10d60 32 ppard DMM1 0x10d64 32 psord DMM1 0x10d68 32 podrd DMM1 0x10d6c 32 pdatd DMM1 0x10d70 32 CPM Timers tgcr1 DMM1 0x10d80 8 tgcr2 DMM1 0x10d84 8 tmr1 DMM1 0x10d90 16 tmr2 DMM1 0x10d92 16 trr1 DMM1 0x10d94 16 trr2 DMM1 0x10d96 16 tcr1 DMM1 0x10d98 16 tcr2 DMM1 0x10d9a 16 tcn1 DMM1 0x10d9c 16 31

32 tcn2 DMM1 0x10d9e 16 tmr3 DMM1 0x10da0 16 tmr4 DMM1 0x10da2 16 trr3 DMM1 0x10da4 16 trr4 DMM1 0x10da6 16 tcr3 DMM1 0x10da8 16 tcr4 DMM1 0x10daa 16 tcn3 DMM1 0x10dac 16 tcn4 DMM1 0x10dae 16 ter1 DMM1 0x10db0 16 ter2 DMM1 0x10db2 16 ter3 DMM1 0x10db4 16 ter4 DMM1 0x10db6 16 SDMA-General sdsr DMM1 0x sdmr DMM1 0x1101c 8 IDMA idsr1 DMM1 0x idmr1 DMM1 0x idsr2 DMM1 0x idmr2 DMM1 0x1102c 8 idsr3 DMM1 0x idmr3 DMM1 0x11034 bdigdb Configuration File For NPW755 (MPC755 + MPC8250) System Shen Rong <rshen@udtech.com.cn> [INIT] init core register WREG MSR 0x MSR -- ME, RI,FP WREG MSR 0x MSR -- FP, RI Chip select FLASH (16bit 8MB) WM32 0x xFF BR0 WM32 0x xFF800Cf6 OR0 WM32 0x xFFFFFF03 SYPCR WM32 0x x BCR WM32 0x x4224C000 SIUMCR 32

33 WM16 0x E 0x556C SWSR WM16 0x E 0xAA39 SWSR >> should be confirmed WM32 0x000101a8 0xF change immr WM32 0xF x BR2 WM32 0xF xF8002AC0 OR2 SDRAM init(sdram machine) WM16 0xF x2000 MPTPR WM8 0xF001019C 0x32 PSRT WM32 0xF x832DA46E PSDMR1 -- normal opt, disable refresh WM32 0xF xAB2DA46E PSDMR2 -- precharge WM8 0x xFF MEM1 -- a write following the precharge WM32 0xF x8B2DA46E PSDMR3 -- CBR refresh WM8 0x xFF MEM2 WM8 0x xFF MEM3 WM8 0x xFF MEM4 WM8 0x xFF MEM5 WM8 0x xFF MEM6 WM8 0x xFF MEM7 WM8 0x xFF MEM8 WM8 0x xFF MEM9 WM32 0xF x9B2DA46E PSDMR4 -- mode register write WM8 0x xFF MEM10 -- mode value WM32 0xF xDB2DA46E PSDMR5 -- enable auto refresh WM32 0xF xC32DA46E PSDMR6 -- normal opt, auto refresh enabled SDRAM init end WM32 0x0 0x WM32 0x4 0x [TARGET] CPUTYPE 8260 the CPU type (603EV,750,8240,8260) 33

34 JTAGCLOCK 0 use 16 MHz JTAG clock WORKSPACE 0x workspace for fast download and cache flush BDIMODE AGENT the BDI working mode (LOADONLY AGENT GATEWAY) BREAKMODE SOFT SOFT or HARD, HARD uses PPC hardware breakpoint MMU XLAT translate effective to physical address PTBASE 0x000000f0 here is the pointer to the page table pointers DCACHE FLUSH VECTOR CATCH catch unhandled exceptions MEMDELAY 2000 additional memory access delay PARITY ON enable data parity generation POWERUP 200 WAKEUP 200 [HOST] IP FILE E:\bdi2000\powerpc\ppcboot.bin FORMAT BIN LOAD MANUAL load code MANUAL or AUTO after reset DEBUGPORT 2001 [FLASH] CHIPTYPE AM29BX16 Flash type AMD29LV640 CHIPSIZE 0x The size of one flash chip in bytes: 8M(e.g. AM29F010 = 0x20000) BUSWIDTH 16 The width of the flash memory bus in bits ( ) FILE 8250_head.bin FORMAT BIN 0xFFE00000 ERASE 0XFE BLOCK ERASE 0XFFE00000 BLOCK WORKSPACE 0x workspace in target RAM for fast download [REGS] DMM1 0x FILE reg8260.def 8 idsr4 DMM1 0x idmr4 DMM1 0x1103c 8 FCC1 gfmr1 DMM1 0x fpsmr1 DMM1 0x ftodr1 DMM1 0x fdsr1 DMM1 0x1130c 16 34

35 fcce1 DMM1 0x fccm1 DMM1 0x fccs1 DMM1 0x ftirr1_phy0 DMM1 0x1131c 8 ftirr1_phy1 DMM1 0x1131d 8 ftirr1_phy2 DMM1 0x1131e 8 ftirr1_phy3 DMM1 0x1131f 8 FCC2 gfmr2 DMM1 0x fpsmr2 DMM1 0x ftodr2 DMM1 0x fdsr2 DMM1 0x1132c 16 fcce2 DMM1 0x fccm2 DMM1 0x fccs2 DMM1 0x ftirr2_phy0 DMM1 0x1133c 8 ftirr2_phy1 DMM1 0x1133d 8 ftirr2_phy2 DMM1 0x1133e 8 ftirr2_phy3 DMM1 0x1133f 8 FCC3 gfmr3 DMM1 0x fpsmr3 DMM1 0x ftodr3 DMM1 0x fdsr3 DMM1 0x1134c 16 fcce3 DMM1 0x fccm3 DMM1 0x fccs3 DMM1 0x BRGs 5-8 brgc5 DMM1 0x115f0 32 brgc6 DMM1 0x115f4 32 brgc7 DMM1 0x115f8 32 brgc8 DMM1 0x115fc 32 I2C i2mod DMM1 0x i2add DMM1 0x i2brg DMM1 0x i2com DMM1 0x1186c 8 i2cer DMM1 0x i2cmr DMM1 0x

36 Communication Processor cpcr DMM1 0x119c0 32 rccr DMM1 0x119c4 32 rter DMM1 0x119d6 16 rtmr DMM1 0x119da 16 rtscr DMM1 0x119dc 16 rtsr DMM1 0x119e0 32 BRGs 1-4 brgc1 DMM1 0x119f0 32 brgc2 DMM1 0x119f4 32 brgc3 DMM1 0x119f8 32 brgc4 DMM1 0x119fc 32 SCC1 gsmr_l1 DMM1 0x11a00 32 gsmr_h1 DMM1 0x11a04 32 psmr1 DMM1 0x11a08 16 todr1 DMM1 0x11a0c 16 dsr1 DMM1 0x11a0e 16 scce1 DMM1 0x11a10 16 sccm1 DMM1 0x11a14 16 sccs1 DMM1 0x11a17 8 SCC2 gsmr_l2 DMM1 0x11a20 32 gsmr_h2 DMM1 0x11a24 32 psmr2 DMM1 0x11a28 16 todr2 DMM1 0x11a2c 16 dsr2 DMM1 0x11a2e 16 scce2 DMM1 0x11a30 16 sccm2 DMM1 0x11a34 16 sccs2 DMM1 0x11a37 8 SCC3 gsmr_l3 DMM1 0x11a40 32 gsmr_h3 DMM1 0x11a44 32 psmr3 DMM1 0x11a48 16 todr3 DMM1 0x11a4c 16 dsr3 DMM1 0x11a4e 16 scce3 DMM1 0x11a50 16 sccm3 DMM1 0x11a54 16 sccs3 DMM1 0x11a

37 SCC4 gsmr_l4 DMM1 0x11a60 32 gsmr_h4 DMM1 0x11a64 32 psmr4 DMM1 0x11a68 16 todr4 DMM1 0x11a6c 16 dsr4 DMM1 0x11a6e 16 scce4 DMM1 0x11a70 16 sccm4 DMM1 0x11a74 16 sccs4 DMM1 0x11a77 8 SMC1 smcmr1 DMM1 0x11a82 16 smce1 DMM1 0x11a86 8 smcm1 DMM1 0x11a8a 8 SMC2 smcmr2 DMM1 0x11a92 16 smce2 DMM1 0x11a96 8 smcm2 DMM1 0x11a9a 8 SPI spmode DMM1 0x11aa0 16 spie DMM1 0x11aa6 8 spim DMM1 0x11aaa 8 spcom DMM1 0x11aad 8 CPM Mux cmxsi1cr DMM1 0x11b00 8 cmxsi2cr DMM1 0x11b02 8 cmxfcr DMM1 0x11b04 32 cmxscr DMM1 0x11b08 32 cmxsmr DMM1 0x11b0c 8 cmxuar DMM1 0x11b0e 16 SI1 Registers si1amr DMM1 0x11b20 16 si1bmr DMM1 0x11b22 16 si1cmr DMM1 0x11b24 16 si1dmr DMM1 0x11b26 16 si1gmr DMM1 0x11b28 8 si1cmdr DMM1 0x11b2a 8 si1str DMM1 0x11b2c 8 si1rsr DMM1 0x11b2e 16 37

38 MCC1 Registers mcce1 DMM1 0x11b30 16 mccm1 DMM1 0x11b34 16 mccf1 DMM1 0x11b38 8 bdigdb Configuration File For NPW755 (MPC755 + MPC8250) System Shen Rong <rshen@udtech.com.cn> [INIT] init core register WREG MSR 0x MSR -- ME, RI,FP WREG MSR 0x MSR -- FP, RI Chip select FLASH (16bit 8MB) WM32 0x xFF BR0 WM32 0x xFF800Cf6 OR0 WM32 0x xFFFFFF03 SYPCR WM32 0x x BCR WM32 0x x4224C000 SIUMCR WM16 0x E 0x556C SWSR WM16 0x E 0xAA39 SWSR >> should be confirmed WM32 0x000101a8 0xF change immr WM32 0xF x BR2 WM32 0xF xF8002AC0 OR2 SDRAM init(sdram machine) WM16 0xF x2000 MPTPR WM8 0xF001019C 0x32 PSRT WM32 0xF x832DA46E PSDMR1 -- normal opt, disable refresh WM32 0xF xAB2DA46E PSDMR2 -- precharge WM8 0x xFF MEM1 -- a write following the precharge WM32 0xF x8B2DA46E PSDMR3 -- CBR refresh WM8 0x xFF MEM2 38

39 WM8 0x xFF MEM3 WM8 0x xFF MEM4 WM8 0x xFF MEM5 WM8 0x xFF MEM6 WM8 0x xFF MEM7 WM8 0x xFF MEM8 WM8 0x xFF MEM9 WM32 0xF x9B2DA46E PSDMR4 -- mode register write WM8 0x xFF MEM10 -- mode value WM32 0xF xDB2DA46E PSDMR5 -- enable auto refresh WM32 0xF xC32DA46E PSDMR6 -- normal opt, auto refresh enabled SDRAM init end WM32 0x0 0x WM32 0x4 0x [TARGET] CPUTYPE 8260 the CPU type (603EV,750,8240,8260) JTAGCLOCK 0 use 16 MHz JTAG clock WORKSPACE 0x workspace for fast download and cache flush BDIMODE AGENT the BDI working mode (LOADONLY AGENT GATEWAY) BREAKMODE SOFT SOFT or HARD, HARD uses PPC hardware breakpoint MMU XLAT translate effective to physical address PTBASE 0x000000f0 here is the pointer to the page table pointers DCACHE FLUSH VECTOR CATCH catch unhandled exceptions MEMDELAY 2000 additional memory access delay PARITY ON enable data parity generation POWERUP 200 WAKEUP 200 [HOST] IP FILE E:\bdi2000\powerpc\ppcboot.bin FORMAT BIN LOAD MANUAL load code MANUAL or AUTO after reset DEBUGPORT

40 [FLASH] CHIPTYPE AM29BX16 Flash type AMD29LV640 CHIPSIZE 0x The size of one flash chip in bytes: 8M(e.g. AM29F010 = 0x20000) BUSWIDTH 16 The width of the flash memory bus in bits ( ) FILE 8250_head.bin FORMAT BIN 0xFFE00000 ERASE 0XFE BLOCK ERASE 0XFFE00000 BLOCK WORKSPACE 0x workspace in target RAM for fast download [REGS] DMM1 0x FILE reg8260.def SI2 Registers si2amr DMM1 0x11b40 16 si2bmr DMM1 0x11b42 16 si2cmr DMM1 0x11b44 16 si2dmr DMM1 0x11b46 16 si2gmr DMM1 0x11b48 8 si2cmdr DMM1 0x11b4a 8 si2str DMM1 0x11b4c 8 si2rsr DMM1 0x11b4e 16 MCC2 Registers mcce2 DMM1 0x11b50 16 mccm2 DMM1 0x11b54 16 mccf2 DMM1 0x11b58 8 BDI2000 telnet BDI LINUX / PPC8270/usr/src/ linux _mvl31 LINUX a) make mrproper b) make pegasus_config PPC82 make menuconfig make xconfig c) make dep d) make uimage uboot 40

41 PPC8270/usr/src/ linux _mvl31.config arch/ppc/configs/ uimage PPC8270/usr/src/ linux _mvl31 arch/ppc/boot/images/ copy /tftpboot FLASH Linux make depmake uimage &>log log vi log 3.3 Linux Linux / root root=/dev/nfs root=/dev/mtdblock/1 mtd root=/dev/ram Ramdisk ext2 ext3 jffs jffs2 romfs(uclinux) cramfs nfs ext2 ext3 Linux FLASH ext2/ext3 Ramdisk jffs jffs2 FLASH romfs cramfs cramfs nfs nfs Linux Linux FLASH FLASH Linux Ram Ramdisk Ramdisk FLASH FLASH U-Boot Linux FLASH ( mkimage ) Ram Ramdisk Ramdisk FLASH Ram FLASH Ramdisk Ram FLASH Ramdisk Ramdisk a) Linux Ramdisk initrd Linux ramdisk PPC8270 Block Device 41

42 PPC82 10Mbytes ramdisk ramdisk b) Linux Ramdisk FLASH c) U-Boot initrd_high Ramdisk Ramdisk Ramdisk Linux U-Boot Linux Linux mem=48m initrd_high 0x Linux Ramdisk FLASH d) bootm bootm 0xfff xff Linux Kernel Image RootFS Image Image FLASH PPC82 MontaVista Linux 100 FLASH 1) Linux 2) 3) MontaVista Devrocket MontaVista Linux kernel Bug 10M Bytes ext2 dd if=/dev/zero of=./root bs=11264k count=1 2>/dev/null mke2fs -F -m0./root tune2fs -c 0./root root 10M Byte 42

43 ext2 mount PPC82 uboot Linux a) mkdir /mnt/ext2 b) mkdir /mnt/root c) mount -o loop /ppc8270/usr/src/ramdisk/root.ext2 /mnt/ext2 d) mount -o loop /ppc8270/usr/src/ramdisk/root /mnt/root e) cd /mnt/ext2 f) tar -cf /tmp/root.tar./* g) cd /mnt/root h) rm -rf * i) tar -xf /tmp/root.tar j) cd /ppc8270/usr/src/ramdisk/ k) umount /mnt/root l) umount /mnt/ext2 m) gzip -9 root n) /ppc8270/usr/src/u-boot-1.1.1/tools/mkimage -A ppc -O Linux -T /ppc8270/usr/src/ramdisk/ramdisk -C gzip -n Pegasus ramdisk image' -d root.gz /ppc8270/usr/src/ramdisk/ramdisk.img n mkimage uboot uboot PPC82 mount./image.sh uboot 3.4 uboot PPC8270 uboot FLASH JTAG FLASH uboot FLASH 0xfff00000 uboot LINUX LINUX LINUX TFTP RedHat9.0 LINUX TFTP Windows tools tftpd32 tftp Uboot Linux uboot doc PPC8270 FLASH 43

44 3.5 Linux MTD MTD Memory Technology Device PC FLASH FLASH MTD MTD.name = RootFS.offset = 1024 << 10.len = 1024 << 10.mask = fs_writable FLASH 1M Byte 1M Byte RootFS RootFS FLASH MTD JFFS2 MTD /dev/mtdblock/0,1,2 root /dev/mtdblock/n n+1 MTD RootFS PPC8270 MTD /ppc8270/usr/src/linux _mvl31/drivers/mtd/maps/pegasus_partition.c Linux 44

45 static struct mtd_partition partition_info[] = { {.name = "initrd(ext2)",.size = 5056 << 10, /* 5MB - 16KB */.offset = 64<<10,.mask_flags = MTD_WRITEABLE, }, {.name = "driver(jffs2)",.size = 2048 << 10, /* 2MB */.offset = 5120 << 10, }, {.name = "uboot,env,linux",.size = 1024 << 10, /* 1MB */.offset = 7168 << 10,.mask_flags = MTD_WRITEABLE, } } FLASH 16K HRCW 4.1 LINUX PC PPC Intel CPU PPC PC minicom ftp jffs2 4.2 UNIX B UNIX LINUX man Makefile /PPC8270/usr/src/application/ Makefile 45

46 /PPC8270/usr/src/application/hello Makefile GCC_FLAGS = -Wstrict-prototypes -Wpointer-arith -Wcast-align -Wcast-qual\ -Wtraditional\ -Wshadow\ -Wconversion\ -Waggregate-return\ -Wmissing-prototypes\ -Wnested-externs\ -Wall # Add -DNO_DAEMON if you do not want the server to fork upon launch # Add -lefence to LDFLAGS to link with ElectricFence # Add -pg to CFLAGS and LDFLAGS to get profiling output with gcc/gprof LDFLAGS = LIBS = CFLAGS = -g -O2 -Wall -I. # Change these if necessary YACC = bison -y LEX = flex CC = ppc_82xx-gcc CPP = ppc_82xx-g++ SOURCES = hello.c OBJS = hello.o #${SOURCES:.c=.o}.PHONY: clean mrclean distclean depend all dist hello: ${OBJS} ${CC} -o $@ hello.o ${LDFLAGS} ${LIBS} clean: rm -f ${OBJS} distclean: mrclean mrclean: clean rm -f Makefile put hello SOURCES = hello.c 46

47 OBJS = hello.o hello: ${OBJS} ${CC} -o $@ hello.o ${LDFLAGS} ${LIBS} make hello hello LINUX FLASH FTP jffs2 PPC8270 /dev/mtdblock/1 /etc/rc.d/rc.local /myapp 4.3 /PPC8270/usr/src/ramdisk/ root.ext2 4.2 ramdisk cd /PPC8270/usr/src/ramdisk/ramdisk mkdir ramdisk root.ext2 mount ramdisk mount o loop root.ext2 ramdisk/ cd ramdisk/ ls bin etc linux mnt sbin usr dev lib lost+found proc tmp LINUX hello cd /ramdisk mkdir application ( ) cd application mkdir hello cd hello cp /PPC8270/usr/src/application/hello/hello. ( hello hello hello / ) cd /PPC8270/usr/src/ramdisk umount ramdisk./image.sh FLASH, : ls application bin etc linuxrc mnt sbin usr dev lib lost+found proc tmp map application cd application cd hello hello hello : 47

48 ./hello 4.4 LINUX ppclinux PC LINUX REDHAT LINUX FOR MMU libc glibc.so FOR PC LINUX REDHAT ppclinux 1. microwin boa 2. Makefile CC PC gcc ppc_82xx-** iptables gcc C ar Makefile KERNEL_DIR=/PPC8270/usr/src/linux _mvl31 CC = ppc_82xx-gcc AR = ppc_82xx-ar linux MMU IO ioremap IO PC8 IO 0 1 IO 2 write_gpio.c gpio_test.c 1 linux/driver/char/ linux/driver/char/ Makefile obj-y += mem.o tty_io.o n_tty.o tty_ioctl.o raw.o pty.o misc.o random.o ppcflash.o gpio_test.o 2 ramdisk dev gpiotest mknod gpiotest c /* driver/char/gpio_test.c * * This file provide IO reading and writing from user space. * Pls create some device file in diretory /dev/gpiotest whose major is

49 * This driver support devices. In user space user can read and write * IO through open and ioctl function provided by glibc. * */ #include <linux/fs.h> #include <linux/iobuf.h> #include <linux/major.h> #include <linux/blkdev.h> #include <linux/capability.h> #include <linux/smp_lock.h> #include <asm/uaccess.h> #include "gpio_test.h" #include <asm/io.h> #include <linux/vmalloc.h> #define dprintk(x...) #define IOPORT_MAJOR 220 typedef char ioport_device_t static ioport_device_t gpio_devices[256] int gpio_open(struct inode *, struct file *) int gpio_release(struct inode *, struct file *) int gpio_ctl_ioctl(struct inode *, struct file *, unsigned int, unsigned long) static struct file_operations gpio_fops = { open: gpio_open, release: gpio_release, } static struct file_operations gpio_ctl_fops = { ioctl: gpio_ctl_ioctl, open: gpio_open, release: gpio_release, } int init gpio_init(void) { int i register_chrdev(ioport_major, "gpiotest", &gpio_ctl_fops) return 0 } initcall(gpio_init) /* * Open/close code for raw IO. */ int gpio_open(struct inode *inode, struct file *filp) { int minor minor = MINOR(inode->i_rdev) 49

50 /* if (ioport_devices[minor].io_lock) { printk("device is busy\n") return -1 }*/ *(volatile unsigned short*)(0xfff x962)&=~0x0080 *(volatile unsigned short*)(0xfff x960) =0x0080 gpio_devices[minor]++ return 0 } // ioremap int gpio_release(struct inode *inode, struct file *filp) { int minor minor = MINOR(inode->i_rdev) if (gpio_devices[minor]) gpio_devices[minor]-- *(volatile unsigned short*)(0xfff x960)&=~0x0080 *(volatile unsigned short*)(0xfff x962) =0x0080 return 0 } /* * Deal with ioctls against the raw-device control interface, to bind * and unbind other raw devices. */ int gpio_ctl_ioctl(struct inode *inode,struct file *flip,unsigned int command,unsigned long arg) { int err = 0 int minor = MINOR(inode->i_rdev) switch (command) { case IOWRITE: *(volatile unsigned short*)(0xfff x966)&=~0x0080 return 0 case IOCLEAR: *(volatile unsigned short*)(0xfff x966) =0x0080 return 0 default: err = -EINVAL } return err } #define DEVICE_PPCFLASH "/dev/gpiotest" int main() { 50

51 } int fd int val=-1 if((fd=open(device_ppcflash,o_rdonly O_NONBLOCK))<0) { perror("can not open device") exit(1) } while(1){ printf("0:set,1:clear,2: quit :") scanf("%d",&val) if(val==0) ioctl(fd,iowrite,0) else if(val==1) ioctl(fd,ioclear,0) else if(val==2){ close(fd) return 0 } else{ printf("val is %d\n",val) continue } } return linux linux linux insmod modprobe rmmod linux.config y m linux/include/linux/autoconf.h 51

52 V 5V 4. JTAG 5. MPC82xx Motorola PowerQuicII 6. CPU 7. 5V ATX 8. 52

53 5.2 53

54 5.3 54

55 5.4 MPC Flash Flash Nor Flash Nand Flash 60x Nor Flash AMD AM29LV064 8MB Flash AMD Flash 16bit Nand Flash PCB Samsung K9Fxx08 Nand Flash 8bit. SDRAM 4 32MB SDRAM 16bit 64bit MPC x 133MHz Mixim MAX708 66MHz CPU SDRAM 55

56 SMC1 DB9 RTC MPC8280 RTC RTC DS1307RTC CPU IIC CPU SCL SDA GPIO PA22 PA23 GPIO IIC 5.6 CS0 BootFlash 0xFF : 8MB CS1 Nand Flash Nand Flash CS2 SDRAM 0x MB CS9 8 LED 0xE Byte J7 J8 J9 J10 CPU : J7->EINT1 J8->EINT2 J9->EINT3 J10->EINT4 5.8 GPIO 6 LED CPU GPIO CPU GPIO LED GPIO LED GPIO LED CPU CPU GPIO LED 56

57 DS13 PA0 DS14 PA1 DS15 PA2 DS16 PA3 DS17 PA4 DS18 PA LED 4 8 LED CS CPU CS9 :0xE LED 3.3V 5V R84 R85 5V LED R85 R84 3.3V LED MD[23..20]4bit 74LS373 4 LED 0 CPU CS9 CPU CS LED 57

58 5.10 FCC1 FCC2 FCC3 CPU FCC1 FCC2 FCC3 MII MDIO MDCLK MDINT 1 MII TX PC22 MII RX PC23 MDIO PA7 MDCLK PA6 MDINT PC11 2 MII TX PC18 MII RX PC19 MDIO PA11 MDCLK PA10 MDINT PC12 3 MII TX PC16 MII RX PC17 MDIO PA12 MDCLK PA13 MDINT PC P1 58

59 P2 59

60 5.12 CPU CPU MPC8280 MPC8280EC.pdf 7.1 0x bit 0B0010 CPU MPC8280EC.pdf Bit[28..31] 60

61 VCC5 4.3V 18V 4.7V 5.5V 2. 5V 220uF 0.1uF 0.1uF 3. LocalBus SMC1RXD (PD8) SMC1TXD (PD9) COM_T COM_R COM_T COM_R RS232 SMC1RXD SMC1TXD TTL COM_T COM_R 61

62 5. /RESET_IN ATX PC HUB PC 62