CYUSB3011 EZ-USB(TM) FX3: SuperSpeed USB Controller

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EZ-USB FX3 SuperSpeed USB µ µ TDI TRST# TMS TCK TDO FSLC[0] FSLC[1] FSLC[2] CLKIN JTAG CLKIN_32 XTALIN XTALOUT DATA[31:0] CTL[12:0] PMODE[2:0] INT# GPIF II ARM926EJ -S Embedded SRAm (512kB) 32 EPs

1 EZ-USB FX3 SuperSpeed USB µ µ TDI TRST# TMS TCK TDO FSLC[0] FSLC[1] FSLC[2] CLKIN JTAG CLKIN_32 XTALIN XTALOUT DATA[31:0] CTL[12:0] PMODE[2:0] INT# GPIF II ARM926EJ -S Embedded SRAm (512kB) 32 EPs HS/FS/LS OTG Host SS Peripheral HS/FS Peripheral US B I NTE RFA CE OTG_ID SSRX - SSRX + SSTX - SSTX + D+ D- RESET # EZ-Dtect I2C UART SPI I2S I2C_SCL I2C_SDA TX RX CTS RTS SSN SCK MISO MOSI I2S_CLK I2S_SD I2S_WS I2S_MSCLK Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number Rev. *A Revised December 18, 2012

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3 CRYSTAL* POWER SUBSYSTEM XTALIN XTALOUT External Processor text (example: MCU/CPU/ASIC/ FPGA) GPIF II EZ-USB FX3 (ARM9 Core) USB Port USB Host Serial Interfaces (example: I2C) * A clock input may be provided on the CLKIN pin instead of a crystal input External Serial Peripheral (example: EEPROM) Document Number Rev. *A Page 3 of 37

4 CRYSTAL* XTALOUT XTALIN EXTERNAL SLAVE DEVICE (Eg: IMAGE SENSOR) GPIF II EZ-USB FX3 (ARM9 Core) USB Port USB Host I2C * A clock input may be provided on the CLKIN pin instead of a crystal input EEPROM EZ-USB FX3 VBATT VBUS OTG_ID SSRX- SSRX+ SSTX- SSTX+ D- D+ USB Interface Document Number Rev. *A Page 4 of 37

5 POWER SUBSYSTEM U3RXVDDQ U3TXVDDQ VIO1 USB Connector VIO2 VIO3 VIO4 CVDDQ VIO5 AVDD VDD GND OVP device VBUS OTG_ID SSRX- SSRX+ SSTX- SSTX+ D- D+ USB-Port EZ-USB FX3 Document Number Rev. *A Page 5 of 37

6 Carkit UART Pass Through Carkit UART pass through interface on GPIF (TM) II interface. Carkit UART pass through interface on GPIOs UART_TXD UART_RXD GPIO[48] (UART_TX) GPIO[49] (UART_RX) USB PHY TXD RXD DP DM Ctrl MUX USB-Port RXD (DP) TXD (DM) External Processor SLCS# PKTEND FLAGB FLAGA A[1:0] D[31:0] SLWR# SLRD# SLOE# EZ-USB FX3 Note: Multiple Flags may be configured. Document Number Rev. *A Page 6 of 37

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13 µ µ µ µ Document Number Rev. *A Page 13 of 37

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15 tclkh tclkl CLK tclk tlz tds tdh tlz tcoe tco tdoh thz tdoh DQ[31:0] - Data (IN) Data1 (OUT) Data2 (OUT) ts th CTL(IN) CTL (OUT) tctlo tcoh Document Number Rev. *A Page 15 of 37

16 tds/ tas tdh/tah DATA/ ADDR DATA IN tchz CTL# (I/P, ALE/ DLE) tctlassert_dqlatch tclz/ toelz taa/tdo tctldeassert_dqlatch tchz/toehz DATA OUT DATA OUT CTL# (I/P, non ALE/ DLE tctlassert tctldeassert tctlalpha ALPHA O/P BETA O/P tctlbeta tctlassert 1 1 tctldeassert tctl# (O/P) 1. n is an integer >= 0 tdst tdht DATA/ ADDR tctldeassert_dqassert CTL# I/P (non DLE/ALE) tctlassert_dqassert tds tctldeassert_dqlatchddr CTL# (I/P) tctlassert_dqlatchddr tdh tds tdh DATA IN Document Number Rev. *A Page 16 of 37

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19 Synchronous Read Cycle Timing t CYC PCLK t CH t CL 3 cycle latency from addr to data 2 cycle latency from SLRD to data SLCS t AS t AH FIFO ADDR An Am t RDS t RDH SLRD SLOE FLAGA (dedicated thread Flag for An) (1 = Not Empty 0= Empty) FLAGB (dedicated thread Flag for Am) (1 = Not Empty 0= Empty) 2 cycle latency from SLRD to FLAG t CFLG t CFLG t OELZ toez t OELZ t CDH t CO t OEZ Data Out High-Z Data driven:dn(an) DN+1(An) DN(Am) D N+1(Am) D N+2(Am) SLWR (HIGH) Document Number Rev. *A Page 19 of 37

20 Synchronous Write Cycle Timing t CYC PCLK t CH t CL SLCS t AS t AH FIFO ADDR An Am twrs twrh SLWR 3 cycle latency from SLWR# to FLAG t CFLG FLAGA dedicated thread FLAG for An (1 = Not Full 0= Full) FLAGB current thread FLAG for Am (1 = Not Full 0= Full) t DS t DH tds t DH t DH 3 cycle latency from SLWR # to FLAG tcflg Data IN High-Z DN(An) DN(Am) DN+1(Am) DN+2(Am) tpes t PEH PKTEND SLOE (HIGH) Synchronous ZLP Write Cycle Timing t CYC PCLK t CH t CL SLCS t AS t AH FIFO ADDR An SLWR (HIGH) PKTEND t PES t PEH FLAGA dedicated thread FLAG for An (1 = Not Full 0= Full) FLAGB current thread FLAG for Am (1 = Not Full 0= Full) Data IN High-Z t CFLG SLOE (HIGH) Document Number Rev. *A Page 20 of 37

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22 SLCS t AS t AH FIFO ADDR An Am t RDl t RDh SLRD SLOE t FLG t RFLG FLAGA dedicated thread Flag for An (1=Not empty 0 = Empty) FLAGB dedicated thread Flag for Am (1=Not empty 0 = Empty) t OE t RDO t OH t OE t RDO t RDO t OH t LZ Data Out High-Z DN(An) DN(An) DN(Am) DN+1(Am) DN+2(Am) SLWR (HIGH) Document Number Rev. *A Page 22 of 37

23 Asynchronous Write Cycle Timing SLCS t AS t AH FIFO ADDR An Am t WRl t WRh SLWR t FLG t WFLG FLAGA dedicated thread Flag for An (1=Not Full 0 = Full) t WFLG FLAGB dedicated thread Flag for Am (1=Not Full 0 = Full) t WR S t WRH t WR S t WRH DATA In High-Z DN(An) DN(Am) DN+1(Am) DN+2(Am) t WRPE t PEh PKTEND SLOE (HIGH) twrpe: SLWR# de-assert to PKTEND deassert = 2ns min (This means that PKTEND should not be be deasserted before SLWR#) Note: PKTEND must be asserted at the same time as SLWR#. Asynchronous ZLP Write Cycle Timing SLCS t AS t AH FIFO ADDR An SLWR (HIGH) PKTEND FLAGA dedicated thread Flag for An (1=Not Full 0 = Full) t PEl t PEh t WFLG FLAGB dedicated thread Flag for Am (1=Not Full 0 = Full) DATA In High-Z SLOE (HIGH) Document Number Rev. *A Page 23 of 37

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25 µ µ µ µ µ tr µ µ µ µ µ µ µ µ Document Number Rev. *A Page 25 of 37

26 µ µ µ µ µ µ µ µ µ µ µ µ µ µ Document Number Rev. *A Page 26 of 37

27 t Thd t Td Document Number Rev. *A Page 27 of 37

28 SSN (output) t ssnh SCK (CPOL=0, Output) SCK (CPOL=1, Output) MISO (input) MOSI (output) t sdd t sck t lead t wsck t wsck t sdi t hoi LSB LSB t d v t di t rf MSB MSB t lag t dis SPI Master Timing for CPHA = 0 SSN (output) SCK (CPOL=0, Output) SCK (CPOL=1, Output) t lead t wsck t sck t wsck trf t lag t ssnh t sdi t hoi MISO (input) LSB MSB t dv t di t dis MOSI (output) LSB MSB SPI Master Timing for CPHA = 1 Document Number Rev. *A Page 28 of 37

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30 VDD ( core ) xvddq XTALIN/ CLKIN XTALIN/ CLKIN must be stable before exiting Standby/Suspend Mandatory Reset Pulse trr Hard Reset trh RESET # trpw twh Standby/ Suspend Source tsby twu Standby/Suspend source Is asserted (MAIN_POWER_EN/ MAIN_CLK_EN bit is set) Standby/Suspend source Is deasserted A U3VSSQ U3RXVDDQ SSRXM SSRXP SSTXP SSTXM AVDD VSS DP DM NC B VIO4 FSLC[0] R_USB3 FSLC[1] U3TXVDDQ CVDDQ AVSS VSS VSS VDD TRST# C GPIO[54] GPIO[55] VDD GPIO[57] RESET# XTALIN XTALOUT R_USB2 OTG_ID TDO VIO5 D GPIO[50] GPIO[51] GPIO[52] GPIO[53] GPIO[56] CLKIN_32 CLKIN VSS I2C_GPIO[58] I2C_GPIO[59] O[60] E GPIO[47] VSS VIO3 GPIO[49] GPIO[48] FSLC[2] TDI TMS VDD VBATT VBUS F VIO2 GPIO[45] GPIO[44] GPIO[41] GPIO[46] TCK GPIO[2] GPIO[5] GPIO[1] GPIO[0] VDD G VSS GPIO[42] GPIO[43] GPIO[30] GPIO[25] GPIO[22] GPIO[21] GPIO[15] GPIO[4] GPIO[3] VSS H VDD GPIO[39] GPIO[40] GPIO[31] GPIO[29] GPIO[26] GPIO[20] GPIO[24] GPIO[7] GPIO[6] VIO1 J GPIO[38] GPIO[36] GPIO[37] GPIO[34] GPIO[28] GPIO[16] GPIO[19] GPIO[14] GPIO[9] GPIO[8] VDD K GPIO[35] GPIO[33] VSS VSS GPIO[27] GPIO[23] GPIO[18] GPIO[17] GPIO[13] GPIO[12] GPIO[10] L VSS VSS VSS GPIO[32] VDD VSS VDD INT# VIO1 GPIO[11] VSS Document Number Rev. *A Page 30 of 37

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33 E3 PWR VIO3 L1 PWR VSS Document Number Rev. *A Page 33 of 37

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35 *D CY USB 3 XXX BZX I Temperature range : Industrial Package type: BGA Marketing Part Number Base part number for USB 3.0 Marketing Code: USB = USB Controller Company ID: CY = Cypress Document Number Rev. *A Page 35 of 37

36 µ µ Document Number Rev. *A Page 36 of 37

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