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Board Design Guidelines for PCI Express Architecture Cliff Lee Staff Engineer Intel

3 Bus Topology Evolution PCI common clock Meet setup/hold timing Multi-drop parallel I/O AGP source synchronous Single strobe, multiple data Match all data to strobes PCI Express* serial differential CONN Embedded clock Point-to-point, match per data pair only Longer route, creative device placement CONN CONN 133MT/s CONN MCH CLK 533MT/s MCH 2.5+GT/s MCH PCI Express* pt-to-pt routing is is straightforward Copyright 2004, PCI-SIG, All Rights Reserved 3

4 800 mv Serial Differential RX TX TX Spec Eye System board Transmitter (TX) & package AC caps D+ D- PCI Express* Connector Interconnect Loss < 13.2 db Jitter < 0.3 UI Add-in card = + TX RX Receiver (RX) & package RX Spec 175 mv Diff. pairs AC coupled Lane-to-lane de-skew Polarity inversion On-chip equalization On-chip terminations 0.7 UI 0.4 UI UI = Unit Interval as defined in PCI Express* Base Spec Copyright 2004, PCI-SIG, All Rights Reserved 4

PCI Express* Routing Trace length matching between pairs is not required Embedded clock & lane-to-lane de-skew simplifies routing rules Longer system board traces

5 PCI Express* Routing Trace length matching between pairs is not required Embedded clock & lane-to-lane de-skew simplifies routing rules Longer system board traces possible TX usually route on top layer AC coupling caps on TX traces x16 Connector Add-in card AC Coupling Caps System board Copyright 2004, PCI-SIG, All Rights Reserved 5

CEM* Interconnect Budget CEM* (Card ElectroMechanical) Spec defines budget allocation Loss and jitter are key parameters Target impedance not as critical Maintain differential pair symmetry Design

6 CEM* Interconnect Budget CEM* (Card ElectroMechanical) Spec defines budget allocation Loss and jitter are key parameters Target impedance not as critical Maintain differential pair symmetry Design tradeoffs: loss vs. trace length, etc. TX System board AC caps Recommended < 12-inch trace length PCI Express* Connector Board CEM Spec Eye Card CEM Spec Eye Add-in card TX Recommended < 3.5-inch Manage loss and jitter to meet budget Copyright 2004, PCI-SIG, All Rights Reserved 6

Stackup Design No new PCB technology required Standard 4-layer stackup 0.

8 Stackup Design No new PCB technology required Standard 4-layer stackup inch thick PCB Microstrip ½ oz Cu plated or, Stripline 1 oz Cu (6+ layers) T = ~62 mils T Follow simple layout rules & design tradeoffs Copyright 2004, PCI-SIG, All Rights Reserved 8

9 Wide pair-to-pair spacing minimize crosstalk Close intra-pair spacing Same geometry for interleaved/non-interleaved Example impedance targets: Single-end Zo of 60 Ω ±15% Differential Impedance of ~100 Ω ±20% Trace Geometry & Impedance Tx w Tx Tx Non-interleaved topology example Rx w Tx Rx Interleaved topology example Tx mil h Microstrip Tx h 20 mil Stripline Tx Tx Copyright 2004, PCI-SIG, All Rights Reserved 9

FR4 Loss Considerations Loss with Stackup: FR4 material Narrow traces Copper roughness Dielectrics with more resin material Non-homogeneous dielectrics Localized Zo variation due to

10 FR4 Loss Considerations Loss with Stackup: FR4 material Narrow traces Copper roughness Dielectrics with more resin material Non-homogeneous dielectrics Localized Zo variation due to material weave Wide differential impedance variation on µstrip traces Etching and plating process Resin Material Glass Material FR4 cross-section Copyright 2004, PCI-SIG, All Rights Reserved 10

11 Trace Length Longer trace length loss ~0.25 to 0.35 db inherent loss per inch for FR4 microstrip traces at 1.25GHz Manage trace lengths to minimize loss Example: 12-inch board, 3.5-inch card lengths max 1.25GHz freq -5.23dB 20-inch line db Example VNA measurements for differential µstrip trace insertion loss Copyright 2004, PCI-SIG, All Rights Reserved 11

12 Trace Symmetry & Matching No matching needed pair-to-pair Match within each differential pair per segment Match overall length 5 mils (recommended) Symmetric routing for each pair Preferred matching Match near mismatch 45 mils Alternative matching Copyright 2004, PCI-SIG, All Rights Reserved 12

13 Bends and Small Serpentines Avoid tight bends No 90 bends; impact to loss and jitter budgets Keep angles >= 135 (α) Maintain adequate air gap A >= 4x the trace width Lengths of B, C >= 1.5x the width of the trace C B α >3w A Serpentines length is at least 3w for jog w S S1 < 2 S Copyright 2004, PCI-SIG, All Rights Reserved 13

14 Package Pin Field Breakout Use side-by-side breakout for package to maintain symmetry Avoid tight bends Side-by-side Best Adjacent w/ small serpentine OK Adjacent w/ bend Fair Diagonal routing Fair Copyright 2004, PCI-SIG, All Rights Reserved 14

15 Reference Plane Full GND plane reference recommended Stitching vias required for layer transition Keep clearance from plane voids Avoid plane splits Avoid trace over anti-pad Plane Void Long trace routes Gnd stitching via Copyright 2004, PCI-SIG, All Rights Reserved 15

16 AC Coupling Capacitors Size: 0402 best, 0603 ok No 0805 size or C-packs Symmetric placement best Cap size: 0.1uF best Same sizes for both D+/D- Cap location: Along Tx pairs on system board Along Tx pairs on add-in card Copyright 2004, PCI-SIG, All Rights Reserved 16

17 Test Points & Vias Minimize via usage Up to 0.25 db loss per via Use via pad size 25 mil, hole size 14 mil; standard anti-pad size of 35 mil Put test points or LAI pads in series (if used) No stubs Place symmetrically Provide GND pads for single-ended probing LAI pads Probe pads GND pads Copyright 2004, PCI-SIG, All Rights Reserved 17

19 Reference Clock Routing Differential clock routing to each device and connector Use the same differential trace geometries Length matching to different devices NOT required! Clock driver requirements: 100MHz with SSC support (e.g. CK410) Choose low jitter components System board terminations only Clock Driver L Ω ±5% Rs L L4 PCI Express Connector PCI Express Card L5 L1' 0.5 max Rs L2' L3' L3 L4' L5' Rt Rt 49.9Ω ±1% Copyright 2004, PCI-SIG, All Rights Reserved 19

20 Connector Layout Connector with standard PTH Connector sizes: x1, x4, x8, x16 Pinout optimized for differential routing & crosstalk reduction Polarity inversion allowed Loss & crosstalk part of system board budget Side B: Tx Improved PTH connector for PCI Express* D- D+ Side A: Rx D+ D- Gnd Gnd Gnd Gnd Gnd= Green TX= Red Rx= Blue Copyright 2004, PCI-SIG, All Rights Reserved 20

21 Power Rails Increased current capability for x16 connector Additional +12V pin; 1.1 Amp per pin capability Helpful grouping of power supply pins Eases power delivery routing ATX power supply connector 2x12 (recommended) Power Rail +3.3V Voltage Tolerance Current +12V Voltage Tolerance Current +3.3Vaux Voltage Tolerance Current: Wake Non-Wake 75W Slot ± 9% (max) 3.0 A (max) ± 8% (max) 5.5A (max) ± 9% (max) 375 ma (max) 20 ma (max) Copyright 2004, PCI-SIG, All Rights Reserved 21

22 Power Consumption CEM* Spec 1.1 allows for 75W cards Available for x16 connectors Allows for performance graphics cards 75W can be fully drawn thru x16 connector Note: 25W at initial power-up (75W after configuration as a high power device) Up to 25W allowed for x1, x4, x8 cards Connector Sizes Standard height 10 W 1 (max) X1 x4/x8 x16 25 W (max) 25 W (max) 25 W 1 (max) Low profile card 10 W (max) 10 W (max) 25 W (max) 1. Max at initial power-up only. 75 W (max) PCI Express* spec support for 75W cards Copyright 2004, PCI-SIG, All Rights Reserved 22

23 Power Delivery Ensure +3.3V & +12V tolerances at add-in card Max of 2%~3% MB +12V voltage drop (e.g. 360mV) Typical power supply = ± 5% drop Balance trace width vs. length Example: 100 mils min trace width, 12 length for +12V with 1oz Cu Proper power decoupling Max current slew rate of 0.1A/µs Suppress high freq coupling noise Tune capacitor type/location to board needs Example uatx +12V layout 2x12 Power Supply Connector Copyright 2004, PCI-SIG, All Rights Reserved 23

Thermal & Acoustic Platforms need to deliver cool air to x16 slot Use side panel vents, ducting 75W card recommendation: 55 o C air temp at graphics

24 Thermal & Acoustic Platforms need to deliver cool air to x16 slot Use side panel vents, ducting 75W card recommendation: 55 o C air temp at graphics card fan intake Use larger fans for better acoustics Cool Air Source Recommended PCI Express* Side Panel Vent Copyright 2004, PCI-SIG, All Rights Reserved 24

system board, card hockey-stick Supports up to 350g for 75W cards OEMs free to innovate

25 Card Retention Card allows for chassis & system board retention Fixed card height & keep outs Hockey-stick near edge fingers 75W Gfx design guideline for retention solution Clip for system board, card hockey-stick Supports up to 350g for 75W cards OEMs free to innovate independent solutions Requires two, 80-mil diameter holes Copyright 2004, PCI-SIG, All Rights Reserved 25

26 Power Delivery - 150W support Additional 2x3 power supply connector on graphics card for +12V Separate power planes from x16 connector s +12V planes on the graphics card Graphics card should meet safety certifications Features still being reviewed: Recommended current limiting at input of Voltage Regulators (VR) on graphics card Card tolerance to nominal input voltage variations between +12V rails Refer to PCI Express* High-End Graphics CEM Specifications Copyright 2004, PCI-SIG, All Rights Reserved 26

27 Card Retention - 150W support Card may use the space of adjacent slot Additional retention required for cards > 350 grams Hockey Stick feature on card is required on 75W cards but optional for High End Graphic cards. Ergonomic issue with double wide card. Limited access to release lever High End Graphics Spec support 150W cards Copyright 2004, PCI-SIG, All Rights Reserved 27

29 Card Edge Fingers Remove ref plane under edge finger pads Better impedance match PRSNT1#, PRSNT2# Pins Layer 2 Ref Plane 1mm shorter: last-mate, first break Hot-Plug support Multiple PRSNT2# pins (x4,x8,x16 cards) Cards must strap PRSNT1# with furthest PRSNT2# signal System board Hot-Plug support optional Outer Layer Differential Pair Signal Traces Layer 3 Ref Plane PRSNT1# to PRSNT2# Strapping Example Outer Layer Edge Fingers Copyright 2004, PCI-SIG, All Rights Reserved 29

30 Card Physical Dimensions End bracket Top edge keep out and fixed height to enable chassis level retention solutions Hockey-stick to allow for new retention solutions Fixed height for I/O cards (allowance for low profile compliance) Chamfer tolerance ±5 degree Copyright 2004, PCI-SIG, All Rights Reserved 30

31 Card Thermal & Acoustic Limit heat re-circulated thru Gfx card heat sink Use shroud to separate fan intake and heat sink exhaust Place fan intake near air source- direct away the exhaust Reduce fan noise and low speed chatter Use diode and/or thermister for fan speed control cool air source (e.g. from chassis vent) intake shroud exhaust exhaust Copyright 2004, PCI-SIG, All Rights Reserved 31

32 Card Thermal - 150W support Exhaust flow of graphic card needs to be managed Recommended that exhaust from graphic card exit to outside of typical ATX Chassis Recommended that graphic card manufacturer and system integrator work together to insure overall system performance Copyright 2004, PCI-SIG, All Rights Reserved 32

Eye diagrams w/ real-time scope 6+ GHz analog bandwidth 20+ Gs sampling bandwidth SIGTEST analysis

34 Compliance Measurements PCI Express* devices generate compliance pattern per spec Signal validation using: Compliance Base Board (CBB) for add-in cards Compliance Load Board (CLB) for system boards Eye diagrams w/ real-time scope 6+ GHz analog bandwidth 20+ Gs sampling bandwidth SIGTEST analysis software PCI Express* connector CBB Example CLB Example Copyright 2004, PCI-SIG, All Rights Reserved 34

Pass/Fail: Max median-to-peak jitter Min eye voltage margin (high/low)

35 Results Analysis Probe locations TX outputs w/ SMA cables (50Ω terminations at scope) SIGTEST software Create transition bit eye Create de-emphasized eye Pass/Fail: Max median-to-peak jitter Min eye voltage margin (high/low) Validate eye diagrams using real time scope Copyright 2004, PCI-SIG, All Rights Reserved 35

37 Summary PCI Express* point-to-point layout is straightforward Manage loss and jitter from PCB to meet CEM* interconnect budget Follow basic layout rules and design tradeoffs to implement typical topologies Improved system & add-in card features for 75W & 150W cards support Validate compliance eye diagrams using compliance boards and real-time scope Copyright 2004, PCI-SIG, All Rights Reserved 37

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