Table of Content 1. RFC 的寫法 ( 使用 PH_IRQ 當作 Timer base) Comparator Power ( V_LVR, V_PAD, VDD2 ) connect... 7 Examples : 1/3 bias... 7 E

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1 Total page 14 Doc No MK9A160P AP Rev. 1.6 文件名稱 MK9A160P 8 Bit Microcontroller AP Note 版次生效日 ECN No. 制修訂者修訂內容概要 李崑旭 Jemmy 新頒 P4 add. Comparator P5 add. Power connect Jemmy Jemmy Jemmy Jemmy Jemmy P6 1/2 Bias LCD P5. 補充說明 power connect P7~10 Key, LCD & Idd P8. 增加 1/4 bias P6. Comparator CP2 & CP3 與 COMx 共用 P14 STATUS bit6 CORE_VDD 使用限制

2 Table of Content 1. RFC 的寫法 ( 使用 PH_IRQ 當作 Timer base) Comparator Power ( V_LVR, V_PAD, VDD2 ) connect... 7 Examples : 1/3 bias... 7 Examples : 1/2, 1/3 & 1/4 bias /2 Bias LCD (new) /2 Bias /3 Bias Key matrix (MK9A35E,MK9A50 & MK9A80 & MK9A160) STROBE(1) STROBE(2) LCD/LED (MK9A35E,MK9A50 & MK9A80 & MK9A160) Idd (MK9A35E,MK9A50 & MK9A80 & MK9A160) Special Purpose Register 2 (9A80 轉 9A160 要特別注意 ) LVD (MK9A35EP,MK9A50P.MK9A80P,MK9A160P) CORE_VDD (MK9A35EP.MK9A80P,MK9A160P)... 14

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4 1. RFC 的寫法 ( 使用 PH_IRQ 當作 Timer base) 新增功能, 設定時間後, 當時間到了, 會自動清掉 enable (enable=0), 停止 (TM2_CNT,TM3_CNT), 而 RFC data 也會被 latch 至 (TM2_LA, TM3_LA) TMn_CTL2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM3_CTL2 ENC CLR_CNT RFC CAPIN1/ RFC_T1 CAPIN0/ RFC_T0 INT_S PWM_OS OV RFC mode IRQ function RFC INT_S TMn IRQ 0 0 No IRQ 0 1 RFC overflow IRQ 1 0 RFC IRQ 1 1 RFC overflow IRQ (1) RFC=0, INT_S=0 TMn 沒有 IRQ 產生, 只能判斷 PH IRQ (2) RFC=0, INT_S=1 TMn 產生 RFC overflow IRQ, 也可以利用 PH IRQ. (3) RFC=1, INT_S=0 TMn 產生 RFC IRQ, 也可以利用 PH IRQ. (4) RFC=1, INT_S=1 TMn 產生 RFC overflow IRQ, 也可以利用 PH IRQ. RFC=0 : MK9A35P, MK9A50P, MK9A80P 當設定 Timer enable, RFC pad 就開始振盪, 但是 timer counter 要等到第一個 PH IRQ 來, 才開始 counter, 所以第一個 PH irq 要捨棄. Timer 不會產生 RFC IRQ ( 只有 overflow IRQ ) RFC=1 : RFC single mode (MK9A80P ) 這個 mode 的 timer source 來自於 PH_CLK (or PH2_CLK), 設定 Timer enable, RFC pad 會開始振盪 PH_CLK x 1.5 的時間後, Timer 才開始計數, timer 本身會產生 IRQ, 且硬體自動濾掉第一個不需要的 IRQ. 也就是, 直接判斷 Timer RFC IRQ, RFC timer source = PH_CLK x 8. 第一次的 IRQ 產生時, TMn_LA 內的 data 就是正確的! 另外,(TMn_CTL1,bit7) enable 會自動停止 ( 被清為 0 ).

5 2. Comparator (1) 當 V- 與 V+ 電壓接近時, Vout 可能產生振盪, comparator 也會一直發生, 此時應該關掉 comparator IRQ. (2) 當 V+ > V- 時, 會產生 comparator IRQF PAD_CTL1 $13 SEG64/ PD[7] SEG63/ PD[6] SEG62/ PD[5] SEG61/ PD[4] SEG60/ PD[3] SEG59/ PD[2] SEG58/ PD[1] SEG57/ PD[0] Bit Bitn=1 Bitn=0 0 SEG57 PD[0] / CP1+ 1 SEG58 PD[1] / CP1-2 SEG59 PD[2] / CPO 3 SEG60 PD[3] /PWM3 4 SEG61 PD[4] + CAPT2A 5 SEG62 PD[5] + INT 6 SEG63 PD[6] / ELP 7 SEG64 PD[7] / ELC Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWM3/ PAD_CTL6 CP_EN CP_OUT CPO_EN CP_S1 CP_S0 PF3C PF1C PD[3] Bit Bitn=1 Bitn=0 1 PF[1] output from /PF[0] input PF[1] normal output 2 PF[3] output from /PF[2] input PF[3] normal output 0 PWM3 PD[3] 5 PD2 work as CPO_OUT PD2 work as I/O 6 CPO_ OUT (Comparator output) 7 enable disable Ps. {PF0,PF1} & {PF2,PF3} 可以當反向器使用. Bit \value CP_S1.CP_S0 CP3+ CP2+ CP1+ No CP3- CP2- CP1- comparator Ps. 只有一個比較器,1 個輸出 (CPO), 不過有三組輸入可以選擇. Pin define PAD_CTL7 CP_S1~0 I/O (PD_DIR PIN condition or PF_DIR) SEG59/PF[4]/ SEG59 X X Segment CPO PF[4] 1 0 input CPO SEG58/PD[1]/ CP1- SEG57/PD[0]/ CP1+ PF[4] 0 0, 0 1, 1 0 X I/O SEG58 X X Segment PF[1] 0 1 X CP1- PF[1] 0 0, 0 1, 1 0 X I/O SEG57 X X Segment PF[0] 0 1 X CP1+ PF[0] 0 0, 0 1, 1 0 X I/O

6 Pin define PAD_CTL7 CP_S1~0 I/O (PD_DIR or PF_DIR) PIN condition COM16//PF[7]/CP3- COM16 X X Segment PF[4] 1 1 input CP3- PF[4] 0 0, 0 1, 1 0 X I/O COM15/PF[6]/CP3+ COM15 X X Segment PF[1] 1 1 input CP3+ PF[1] 0 0, 0 1, 1 0 X I/O COM14//PF[5]/CP2- COM14 X X Segment PF[4] 1 0 input CP2- PF[4] 0 0, 0 1, 1 0 X I/O COM13/PF[4]/CP2+ COM13 X X Segment PF[1] 1 0 input CP2+ PF[1] 0 0, 0 1, 1 0 X I/O Ps. (1) CP1+/ CP1- : 當選為 comparator input 時, 會比 (CP2+/ CP2-, CP3+/ CP3-) 省電, 不管 PD_DIR 如何設定, PULL 不會開啟, 也無法由 Port 讀到 Hi/Low 電壓. (2) CP2+/ CP2- : 當選為 comparator input 時, 會比 (CP1+/ CP1-) 耗電, PF_DIR 必須設為 input, 可以由 Port 讀到 Hi/Low 電壓. (3) CP3+/ CP3- : 與. (CP2+/ CP2- ) 相同

7 3. Power ( V_LVR, V_PAD, VDD2 ) connect V_LVR 提供內部 LVR & LVD power V_PAD I/O PAD power Internal VDD 來自 VDD2 or VDD1 燒錄時, (VDD2, V_PAD & V_LVR ) 要接在一起. Examples : 1/3 bias

8 Examples : 1/2, 1/3 & 1/4 bias Li mode 1/3 bias Li mode 1/2 bias CUP2 CUP1 VDD1 VDD MK9A160P VDD3 Vdd CUP2 CUP1 VDD1 VDD MK9A160P VDD3 Vdd VDD4 VDD4 Li mode 1/4 bias CUP2 CUP1 CUP0 VDD1 VDD MK9A160P VDD3 VDD4 Vdd

9 4. 1/2 Bias LCD (new) 1/2 Bias COM1 COM2 COM3 COM4 SEGn LCD ON LCD OFF 1/3 Bias COM1 COM2 COM3 COM4 SEGn LCD ON LCD OFF

10 5. Key matrix (MK9A35E,MK9A50 & MK9A80 & MK9A160) MK9A50 MK9A35EP MK9A80 MK9A160 STROBE (1) (2) (2) (2) I/O pull-down 100K 100K 100K 100K Key strobe Pull-down 100K 10K 10K 100k STROBE(1) MK9A50 : STROBE($34h) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STROBE KIEN1 KIEN0 KOAEN KOEN KO3 KO2 KO1 KO0 Bit7~6 (KIEN1~0): Key mode select Bit \value KIEN1~0 Hardware mode 2 Hardware mode 1 Software mode OFF MODE/FUNCTION SEG1~16 PORT PA0~6 & PORT PD3~4 IRQ PC0~7 Hardware mode 2 X Pull down enable X V Hardware mode 1 Hi output Pull down enable X V Software mode X Pull down enable Pull down enable X KOAEN SEG1~16 : Hi output X X X KOEN SEGn : Hi output Others : Floating X X X (1) 省電. 有 IRQ 可以使用 (2) Key (or I/O ) Pull-down resister =100K

11 STROBE(2) MK9A35E/MK9A80/MK9A160 STROBE ($34h) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STROBE FRAME EN KOAEN KOEN KO3 KO2 KO1 KO0 MODE/FUNCTION SEG1~16 PORT PD[0~7] & PORT PA[0~6] PC[0:1] EN X Pull down enable Can t connect to SEGn KOAEN SEG1~16 : Hi output X X KOEN SEGn : Hi output Others : Floating X X (1) Bit7 Frame : read only (2) Software mode only (3) Frame=1 時, 讀 key 會比較省電 (3) Mk9A35E/MK9A80 :Key Pull-down=10K, I/O pull-down=100k 當 key 的電阻大於 2K 時, 會認不到 key. (4) Mk9A160 :Key Pull-down & I/O pull-down=100k 6. LCD/LED (MK9A35E,MK9A50 & MK9A80 & MK9A160) LCD2~0 MK9A50 MK9A35EP MK9A80 MK9A160 X 0 0 1/3 bias 1/3 bias 1/3 bias 1/3 bias X 0 1 Led 3 1/2 bias # 1/2 bias 1/2 bias X 1 0 Led 2 Led 2 Led 2 Led 2 X 1 1 Led 1 Led 1 Led 1 Led x x x 1/4 bias Duty 1/N 4,5,6,7,8 2,3,4,5,6,7 2,3,4,5,6,7,8 2,3,4,5,6,7,8, 10,12,16 (1) MK9A35E/50/80 : 沒有 LCD2 這個 bit (2) MK9A50 Led3 : ICE 上必須要放 100-pin MK9A50 display. (3) MK9A35E 1/2 bias 波形與 MK9A80/160 不同, 某些玻璃會有殘影, 使用此功能必須使用 100-pin MK9A35E display. (4) VDD2 接 VDD 時, 1/2 bias : VDD1=VDD/2, VDD2=VDD3=VDD4=VDD 1/3 bias : VDD1=VDD/2, VDD2=VDD, VDD3=VDD4=VDD *3/2 1/4 bias : VDD1=VDD/2, VDD2=VDD, VDD3=VDD*3/2, VDD4=VDD * 2.

12 7. Idd (MK9A35E,MK9A50 & MK9A80 & MK9A160) 省電模式的設定 MK9A50 MK9A35EP MK9A80 MK9A160 STATUS bit6 x Bit6=1 Bit6=1 Bit6=1 LV 1.5,1.7& 2V 2V (fix) 2V (fix) 1.5,1.7& 2V Config bit12 x bit12=1 bit12=1 bit12=1 LCD_CTL Bit5.4=11 Bit5.4=11 Bit5.4=11 Bit5.4=11 bit5.4 Idd 2uA uA (no LVR) Idd 2.3uA 1.7uA 1.4uA 1.4uA (include LVR) LVR 0.3uA 0.3uA 0.3uA 0.3uA 8. Special Purpose Register 2 (9A80 轉 9A160 要特別注意 ) WBANK ($2Eh) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WBANK WKMB3 WKMB2 WKMB1 WKMB0 -- SPEC DP1 DP0 Bit4 (WKMB0): Working RAM bank select Bit2~0 Bank RAM Display RAM BANK 1 (64 bytes) Display RAM BANK 2 (64 bytes) Reserved Reserved 1 X X Special register (2) (1) 9A160P register 6E,6F,70~7F 是屬於 Special register (2), 跟 display RAM 共用位置, 9A80P 73~7F 則是獨立的位置 (2) Example: #DEFINE RAM_80 80H ORG 00 ;; LGOTO START ORG 100h START: BS WBANK,b2 ;; 設定 register 2 CLR STATUS MOVLA 02h MOVAM LBASDT DISPLAY: BC WBANK,b2 ;; 取消 register 2. ;; data 寫入 display ram BS WBANK,b2 ;; 設定 register 2 ret ;; exit LCD

13 9. LVD (MK9A35EP,MK9A50P.MK9A80P,MK9A160P) LVD 部分測試加測 2.56V 這一階, 範圍 2.45~2.70 不過考量儀表的誤差, spec. 範圍訂為 2.40~2.75V VBLVD1B LVD voltage 3V SYS_CTL bit4.3= V VBLVD2 LVD voltage 3V SYS_CTL bit4.3= V VBLVD3B LVD voltage 3V SYS_CTL bit4.3= V

14 10. CORE_VDD (MK9A35EP.MK9A80P,MK9A160P) STATUS Bit Symbol Description 6 CPU_VDD CPU_VDD: Internal CORE voltage switch ( 3V mode ) 1: 1.5V 0: 3V CPU_VDD=1 Internal 1.5Mhz VDD1 > 1.3V Internal 700Khz VDD1 > 1.2V Internal 32Khz VDD1 > 1.1V

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