16440B_0212

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1 : LOK IRM : PLTFORM : Penryn- (HOST US) : Penryn- (POWR/N) : antiga- (HOST US) : antiga- (MI/V) : antiga- (R) : antiga- (POWR-) : antiga- (POWR-) : antiga- (VSS) : R_SOIMM : R_SOIMM : R_Termination : H&TV-OUT onnector : VI-LVLSHIFT : LOK N (RTMT-) : V, LVS,L,TV,US SW : IHM- (PU/I/zalia) : IHM- (PI/US/PI/MI) : IHM- (SM US/PIO) : IHM- (POWR/N) : K//uP (N-LFQP) : H,ROM,IR & US N. : O ardreader : Newcard : PI LN (INTL LM) : MINI_PI, L, SW : M, TPM, FN,SPI FLSH ROM : udio (MP for N) : udio mp. & Jacks : Super I/O&Port Replicator : M_attery select : M_attery harger : M_System Power : R RM POWR,.V : M_VTT,.V : M_raphics ore : M_PU power : Screw/MI : Non_Footprint for OM : Power Sequency- : Power Sequency- : Power_iagram(& attery) : Power_iagram(Only attery) : MT LOK IRM : Hardware History : LUNH OR(N)_ : LUNH OR(hannel)_ : US*&RJ_ : FPR&Touch Pad_ : Topology : New power states -dapter IN Port Replicator Low Speed I/O udio -Sub Page LN Vidio US Port LN onneter HP&SPIF MI Internal SPK Internal MI Page R - -Sub R - ock VI (TMS) Level Shift Page HP(Port Replicator) MS- series Ver :. TV Out Page LN Switch (PIL) Page us Switch TV/RT Select (IT/QSS) Page MINI PI onn. Page M Page Serial & Parallel US PS* (K/ & Mouse) H Page MS/MS Pro/S/SIO/MM/x I- Page (O OZ) LVS Page PI-LN (LM) Page MINI PI onn. Page PI-xpress LH SPIF Page ~ MI INT SPK SPI Flash INT MI HP_(P/R) M HP_(Jack) Page SPI Flash M Page antiga M - R PI- x antiga M - LVS PI- x antiga M - VI PI LI / PI- LI zalia SPI Penryn INTL antiga PM/M M Super I/O (NS/P-VS) Page ~ Page INTL IHM- SOUTH RI FIR Page Page, NORTH RI Page ~ HOST FS // MHz MI Interface (x/x) K N Page ual hannel RII / MHZ ual hannel RII / MHZ ST ST PI-xpress US,,, Page On board US onnectors SPI US, Page Mini_PI x JK & Selector Page R-SOIMM Page R-SOIMM Page H Page O Page NWR Page LP US TP & K Page Keyboard Touch Pad Smart Fan PU & System Smart Fan SPI IOS Page SYS POWR US Page Fingerprint US./. /MHZ HOST MHZ PI MHZ PI US Page luetooth V V TPS Page _VSUS _VRUN TPS Page VTT(.V).VRUN.VM TPS Page PU POWR ISL Page HRR MTI Page LP UU Page VF_OR ISL Page US Page Port replicator LK N (RTMT-) Page LOK IRM Size ocument Number Rev ustom MS-.VRUN M Page SMR_VTRM RTPS Page.VM PL Page US Page Web M (hannel Optional) MHZ RYSTL MSI ORPORTI MHZ S Tuesday, February, ate: Sheet of

2 Voltage Rails Voltage PWR_SR escription PTR OR TTRY IN OR OK IN ontrol Signal POWR STTS SINL STT SLP_S# SLP_S# SLP_S# S_STT# SLP_M# V*LWYS V*SUS V*M V*RUN locks VLW VLW VSUS_U.V always on power rail.v always on power rail.v lways SUS power PWR_SR PWR_SR SUS_ S( Full ) / M S( Suspend to RM) / M S( Suspend to isk) /M S / Soft / M VSUS.V power rail SUS_ S( Suspend to RM)/M _VIMM SMR_VTRM VSUS.V power rail R.V R Termination voltage.v power rail PM_SLP_S PM_SLP_S PM_SLP_S S( Suspend to isk)/m S / Soft / M Note : WHN MO, System turn on then V*SUS will always keep high **Power states follow page ** _VM.V power rail MT PM_SLP_M VMLK V power rail for MT lock enerator PM_SLP_M VRUN.V switched power rail PM_SLP_S(RUN) VRUN.V switched power rail PM_SLP_S(RUN) VM_WOL LN chip power rail LN_WOL_N & PM_SLP_M _VRUN.V power rail PM_SLP_S _VRUN(VTT). rail for Processor & M I/O PM_SLP_S VHOR ore Voltage for Processor VR_ VF_OR raphic core of MH switched power rail F_VR_N V.V Power rail udio codec VSUS(RUN).VRUN.V power rail H(TVOUT) VRUN MSI ORPORTI PLTFORM Size ocument Number Rev ustom MS- Tuesday, February, ate: Sheet of

3 H_#[:] H_RS#[:] H_RQ#[:] H_#[:] H_RS#[:] H_RQ#[:] U H_# J H_# []# S# H H_S# L VTT H_# []# NR# H_NR# L H_# []# PRI# H_PRI# K H_# []# M IRR# R R H_# []# FR# H U H_FR# H_#[:] H_#[:] N H_# H_# H_# []# RY# F H_RY# J HTMS H_# H_# H_# []# SY# R.R% []# []# Y H_SY# F H_# []# []# N H_# H_# []# HTI H_# []# []# V P H_# H_# []# R# F R.R% H_RQ# H_# []# []# V P H_# H_# []# F L IRR# PRQ# H_# H_# H_# []# IRR# R.R% []# []# V H_# []# []# T P H_# H_# []# INIT# H_INIT# R use ohm if unused. P H_PROHOT# R R H_# []# []# U H_# H_# []# H_# []# []# U R H_# H_LOK# Otherwise, put ohm. []# LOK# H K HTK R.R% H_# []# []# Y H_# H_ST# M ST[]# H_# []# []# W H_# H_RQ# RST# H_PURST# J K H_RS# HTRST# H_# H_# H_RQ# RQ[]# RS[]# F R.R% []# []# Y J H_RS# H_# []# []# W H H_# H_RQ# RQ[]# RS[]# F H H_RS# H_# []# []# W K H_# H_RQ# RQ[]# RS[]# F H_# []# []# J H_# H_TRY# H_RQ# RQ[]# TRY# K H_# []# []# L H_# RQ[]# R put ohm if unused H []# []# H_HIT# H_STN# H_STN# H_# HIT# J STN[]# STN[]# Y Y H_HITM# / change to. ohm/-% H_STP# H_STP# H_# []# HITM# H STP[]# STP[]# U H_INV# H_INV# H_# []# H INV[]# INV[]# U R H_#[:] H_# []# PM[]# W H_#[:] H_# []# PM[]# U H_# H_# H_# []# PM[]# N H_# []# []# Y H_# H_# []# PM[]# K H_# []# []# U H_# H_# []# PRY# P PRQ# H_# []# []# R H_# H_# []# PRQ# R T HTK VTT H_# H_# H_# []# TK []# []# L HTI H_# []# []# T H_# H_# []# TI M W H_# H_# H_# []# TO []# []# L W HTMS H_# H_# H_# []# TMS []# []# M HTRST# H_# []# []# Y H_# H_# []# TRST# R P H_# []# []# F U H_# H_# []# R# KR% P H_# []# []# V H_# H_# []# P H_# []# []# W H_# H_# []# T THRML H_# []# []# H_# H_# []# R Within." H_# []# []# H_# H_# []# L H_PROHOT# H_# []# []# H_# []# PROHOT# T THRM H_# H_# H_ST# V ST[]# THRM []# []# F R N THRM THRM []# []# KR% H_STN# L STN[]# STN[]# H_STN# H_M# M# H_STP# M H_STP# PM_THRMTRIP# STP[]# STP[]# F H_FRR# FRR# THRMTRIP# PM_THRMTRIP#, H_INV# N INV[]# INV[]# H_INV# H_INN# INN# TLRF OMP TST OMP[] R R.R% TLRF OMP H_STPLK# STPLK# R.R% TST TST MIS OMP[] U OMP H_INTR LINT H LK R.R% TST OMP[] OMP H_NMI LINT LK[] TP TST LK_PU_LK TST H_SMI# SMI# LK[] TP OMP[] Y R.R% TST LK_PU_LK# F R R TP TST TST F H_PRSTP#,, TP RSV_ M _KR _KR TP TST TST PRSTP# H_PSLP# RSV_ RSV[] N TP PSLP# TP TST H_PWR# TP RSV_ RSV[] TST PWR# T H_PWR RSV_ RSV[] PU_SL TP SL[] PWROO V H_PUSLP# RSV_ RSV[] PU_SL SLP# TP SL[] TP RSV_ RSV[] TP SL[] PSI# PSI# TP RSV_ RSV[] ZIF-SOKT-RH- TP RSV_ RSV[] TP RSV_ RSV[] F RSV[] Within." mils Spacing VRUN SM us pull high change to.kr TST OMP, --> mils ap close to ZIF-SOKT-RH- OMP, --> mils VRUN thermal SM_PU_LK R.KR VRUN sensor SM_PU_T R.KR THRM U _.U SM_PU_LK LRT#, RSMRST# V SMLK SM_PU_LK Trace : // R _.KR R _MR SM_PU_T SMT SM_PU_T P For LM thermal sensor reserved Q R THRM LRT# - LRT# _KR _N PM_THRMTRIP# R _R T_RIT_# N Q SNSR-M--ZL-TR-RH MSI ORPORTI _.U _N.U PNRYN- (HOST US) Reserve Reserve RSMRST#?? lose to PU socket Size ocument Number Rev For vendor recommend ustom S R ROUP_ R ROUP_ IH RSRV S P/ITP SINLS TROL heck value!! T RP T RP T RP T RP MS- ate: Tuesday, February, Sheet of

4 _VRUN VTT V_OR V_OR V_OR V_OR V_OR V_OR V_OR VTT VSNS VSSSNS PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI Size ocument Number Rev ate: Sheet of MS- PNRYN- (POWR/N) MSI ORPORTI ustom Tuesday, February, Size ocument Number Rev ate: Sheet of MS- PNRYN- (POWR/N) MSI ORPORTI ustom Tuesday, February, Size ocument Number Rev ate: Sheet of MS- PNRYN- (POWR/N) MSI ORPORTI ustom Tuesday, February, close to cpu socket Trace width = mils Trace spacing = mils other spacing = mils length matched within mils Place R close to PU within " Place ap close to pin (m) () (.) Trace width > U. U..U.U U. U..U.U _U. _U..U.U UY UY U. U. U. U. _U. _U..U.U _U. _U. U. U. U. U. _U. _U..U.U U. U. _U. _U. _U. _U. U ZIF-SOKT-RH- U ZIF-SOKT-RH- V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] F V[] F V[] F V[] F V[] F V[] F V[] F V[] F V[] F V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] F V[] F V[] F V[] F V[] F V[] F V[] F V[] F V[] VP[] J VP[] K VP[] M VP[] J VP[] K VP[] M VP[] N VP[] N VP[] R VP[] R VP[] T VP[] T VP[] V VP[] W VSNS F VI[] VI[] F VI[] VI[] F VI[] VI[] F VI[] VSSSNS V[] VP[] VP[] V U. U. U ZIF-SOKT-RH- U ZIF-SOKT-RH- VSS[] P VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] VSS[] VSS[] VSS[] VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[] VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] VSS[] VSS[] VSS[] VSS[] P VSS[] P VSS[] R VSS[] R VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[] U VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] F.U.U U. U. U. U. U. U. U. U. U. U. _U.SP-LF _U.SP-LF _U. _U. U. U. R% R R% R U. U. U. U..U.U U. U. U. U. U. U. U. U. U. U. _U. _U. U. U. U. U. R% R R% R U. U.

5 U H_#[:] H_# H_#[:] H_# H_#_ F H_# H_# H_#_ H_#_ H_# H_# H_#_ H_#_ F F H_# H_# H_#_ H_#_ H H_# H_# H_#_ H_#_ H_# H_# H_#_ H_#_ M H H_# H_# H_#_ H_#_ J H H_# H_# H_#_ H_#_ P F H_# H_# H_#_ H_#_ R H_# H_# H_#_ H_#_ N H H_# H_# H_#_ H_#_ M M H_# H_# H_#_ H_#_ M H_# H_# H_#_ H_#_ P J H_# H_# H_#_ H_#_ F J H_# H_# H_#_ H_#_ N H_# H_# H_#_ H_#_ J H_# VTT H_# H_#_ H_#_ J P H_# H_# H_#_ H_#_ L H_# H_# H_#_ H_#_ H R H_# H_# H_#_ H_#_ J N H_# H_# H_#_ L R H_#_ L H_# H_# H_#_ R% H_#_ M H_# H_# H_#_ H_#_ J H_# H_# H_#_ H_#_ L Trace : mils N H_# H_SWIN H_# H_#_ H_#_ Place ap R H_# H_# H_#_ H_#_ J H_# close to N H_# H_#_ H_#_ H N H_# pin H_# H_#_ R H_#_ P H_# H_# H_#_ K R% H_#_ H_# N H_# H_#_ H_#_.U L H_# H_# H_#_ H_#_ F N H_# H_# H_#_ H_#_ K M H_# H_# H_#_ H_#_ L Y H_# H_#_ H_S# H_# H_#_ H_S# H Y H_ST# H_# H_#_ H_ST#_ Y H_ST# H_# H_#_ H_ST#_ Y H_NR# H_# H_#_ H_NR# Y H_PRI# H_# H_#_ H_PRI# F Y H_RQ# H_ROMP H_# H_#_ H_RQ# W H_FR# H_# H_#_ H_FR# H_SY# H_# H_#_ H_SY# Y LK_MH_LK H_# HPLL_LK H R H_#_ LK_MH_LK# Trace to pin H_# HPLL_LK# H.R% H_#_ H_PWR# H_# H_#_ H_PWR# J within." H_RY# H_# H_#_ H_RY# F Spacing H_HIT# H_# H_#_ H_HIT# H H_HITM# mils H_# H_#_ H_HITM# H_LOK# H_# H_#_ H_LOK# H H_TRY# H_# H_#_ H_TRY# H_# H_#_ H_# H_#_ H_# H_#_ H_# H_#_ H_INV# H_INV# H_# H_#_ H_INV#_ J H_INV# H_INV# H_# H_#_ H_INV#_ L H_INV# H_INV# H_# H_#_ H_INV#_ Y F H_INV# H_INV# H_# H_#_ H_INV#_ Y H_# H_#_ H_STN# H_STN# H_# H_#_ H_STN#_ L H_STN# H_STN# H_# H_#_ H_STN#_ M H_STN# H_STN# H_# H_#_ H_STN#_ H_STN# H_STN# H_# H_#_ H_STN#_ H_# H_#_ H_STP# H_#_ H_STP#_ L H_STP# H_STP# H_STP#_ M H_STP# H_STP# H_STP# H_SWIN H_STP#_ H_STP# H_STP# H_ROMP H_SWIN H_STP#_ H_ROMP H_RQ#[:] H_RQ# H_RQ#_ H_RQ# VTT H_RQ#_ K H_RQ# elete JN and short directly H_RQ#_ F H_RQ# H_RQ#_ H_RQ# H_PURST# H_PURST# H_RQ#_ H_PUSLP# R H_PUSLP# H_RS# H_RS#[:] KR% H_RS#_ H_RS# H_RS#_ F H_RS# H_RS#_ H_VRF H_VRF R KR% _.U Place ap close to pin Trace : mils NTI_PM HOST NTI- (HOST US) Size ocument Number Rev MS- MSI ORPORTI ate: Tuesday, February, Sheet of

6 U _VIMM TP RSV M TP RSV RSV N RSV S_K_ P TP RSV M_LK_R R R TP RSV S_K_ T U RSV M_LK_R T.R% RSV S_K_ V M_LK_R / R change to.k ohm by SL. TP RSV H TP RSV RSV S_K_ U M_LK_R H _VM TP RSV RSV H L_KLT_TRL RSV M_LK_R# Trace within." TP S_K#_ R TP RSV L L_KLT_TRL H P_OMP R.R% RSV RSV S_K#_ R M_LK_R# Trace : mils L_M TP TP L_TRL_LK L_KLT_N P_OMPI T K M_JT_TK RSV S_K#_ U M_LK_R# M TP L_TRL_LK P_OMPO T L M_JT_TI RSV S_K#_ V TP M_LK_R# K R TP L_TRL_T R change to. ohm % ohm TP M_JT_TO RSV M.R% LVS_LK_M# L_TRL_T N M_JT_TMS M_K, N_RN TP RSV S_K_ K L LK P_R#_ H M RSV M_K, LVS_T_M by Intel. sch RSV S_K_ Y J TP L T P_R#_ J T RSV S_K_ Y M_K, _VIMM P_R#_ L RSV M_K, LVS_VN_M TP S_K_ P_R#_ L TP RSV RSV M LVS_I P_R#_ N RSV M_S#, R is for SVO TVLK TP S_S#_ R.KR%- L_V_N RSV LVS_V P_R#_ P M S_S#_ Y TP LVS_I RSV M_S#, LVS_V P_R#_ N S_S#_ V M_S#, RSV M_S#, Place ap close to TP S_S#_ R R LVS_VRFH P_R#_ T Y KR% LVS_VRFL P_R#_ U RSV pin Trace : mils LVS_TLLKN_M LVS_LK# P_R#_ Y S_OT_ M_OT, LVS_TLLKP_M LVS_LK P_R#_ Y S_OT_ Y M_OT, LVS_TULKN_M LVS_LK# P_R#_ Y RSV M_OT, LVS_TULKP_M TP S_OT_ F LVS_LK P_R#_ RSV S_OT_ Y TP RSV M_OT, F P_R#_ LVS_TLN_M RSV RSV H TP H SM_ROMP.U.Y LVS_TLN_M TP RSV SM_ROMP.u LVS_T#_ P_R#_ RSV F SM_ROMP# SM_ROMP# H R LVS_T#_ P_R#_ RSV LVS_TLN_M.KR% LVS_T#_ N_RP SM_ROMP_VOH SM_ROMP_VOH F LVS_T#_ P_R_ H SM_ROMP_VOL P_R_ J SM_ROMP_VOL H LVS_TLP_M H LVS_T_ P_R_ L LVS_TLP_M SM_VRF LVS_T_ P_R_ L SM_VRF V LVS_TLP_M F JN _NR SM_PWROK R LVS_T_ P_R_ N R R% R SM_RT F.U.Y.u LVS_T_ P_R_ P KR% P_R_ N SM_RMRST# TP LVS_TUN_M LVS_T#_ P_R_ T N_RP LVS_TUN_M H PLL_RF_LK LVS_T#_ P_R_ U RFLK LVS_TUN_M LVS_T#_ P_R_ Y PLL_RF_LK# RFLK# J PLL_RF_SSLK LVS_T#_ P_R_ W RFSSLK _VIMM P_R_ Y PLL_RF_SSLK# F RFSSLK# LVS_TUP_M LVS_T_ P_R_ LVS_TUP_M P_LK F LVS_T_ P_R_ LK_PI_PLL LVS_TUP_M F LVS_T_ P_R_ P_LK# LK_PI_PLL# K P_R_ R LVS_T_ Place ap close to KR% RN N_TN _.U V_RN PR-R P_T#_ J N_TN _.U pin Trace :mils P_T#_ M V_RN N_TN MI_RN_ MI_TN F _.U TV_ P_T#_ M V_RN N_TN MI_RN_ MI_TN H _.U TV_ P_T#_ M V_RN N_TN _.U MI_RN_ MI_TN K TV_ P_T#_ M V_RN N_TN _.U MI_RN_ H MI_TN V_RN R P_T#_ R H N_TN V_RN KR% N_TN _.U MI_RP_ P_T#_ N _.U TV_RTN MI_TP V_RN.U MH_SL T F_ MI_RP_.U P_T#_ T MI_TP P_T#_ U MH_SL R F_ MI_RP_ MI_TP P_T#_ U P F_ MI_RP_ H MI_TP TV_SL_ P_T#_ Y P F_ Follow design guide p. TV_SL_ P_T#_ T~ is for H TV output P MI_RN F_ F_ MI_TN_ R TV disable and RT enable P_T#_ MI_RN T~ is for VI- level-shift F_ F_ MI_TN_ KR P_T#_ N MI_RN F_ F_ MI_TN_ P_T#_ M F_ MI_TN_ H MI_RN P_T#_ F_ F_ N_TP F_ MI_TP_ MI_RP V M _.U V_RP N_TP F_ MI_TP_ R R% RT_LU P_T_ J MI_RP P_T_ L _.U V_RP N N_TP _.U F_ MI_TP_ F MI_RP V M V_RP P N_TP _.U F_ MI_TP_ H R R% RT_RN P_T_ M MI_RP P_T_ M V_RP T N_TP _.U F_ V_R_M J P_T_ M V_RP R R R% RT_R N_TP _.U F_ P_T_ R V_RP M N_TP V_RP F_ F.U RT_IRTN P_T_ N L N_TP _.U F_ P_T_ T V_RP H F_ V_LK_M H RT LK P_T_ U P V_T_M F_ F_ J P_T_ U R R R RT T V_HSYN_M F_ F_ J RT_HSYN P_T_ Y T F_ F_VI_ F_VI_ R R RT_TVO_IRF P_T_ Y F_VI_ F_VI_ V_VSYN_M L RT_VSYN P_T_ F_VI_ F_VI_ P_T_ F_VI_ PM_SYN# F_VI_ F P_T_ PM_SYN# R JN _NRPM_PRSTP#_R PM_SYN# F_VI_ TP P_T_,, H_PRSTP# PM_TTS# PM_PRSTP# PM_TTS# N R PM_TTS# PM_T_TS#_ PM_TTS# P NTI_PM JN _NRN_PWR PM_T_TS#_ LVS_TLLKN_M LVS_TULKN_M,, IMVP_PWR T F_VR_N N_RST# PWROK F_VR_N R% _VM N_RST# T PM_THRMTRIP# RSTIN#, PM_THRMTRIP# T JN _NRPRSLPVR_R THRMTRIP# RI, PM_PRSLPVR R RI PRSLPVR _R _R L_LK Place ap R L_LK H / R change to ohm for driving nhanced KR% LVS_TLLKP_M LVS_TULKP_M L_T close to pin VRUN L_T H N_ L_PWROK N MPWROK, F SVO_TRLLK LVS_TLN_M LVS_TLN_M L_RST# R KR PM_TTS# N_ L_RST# J L_VRF R KR PM_TTS# N_ L_VRF H SVO_TRLT I N_ H R RI RI R KR LK_MH_O# N_ I N R _R R% N_ P_TRLLK N P_TRLLK H.U LVS_TLP_M LVS_TLP_M N_ P_TRLT M P_TRLT F LVS_LK_M# R R N_ SVO_TRLLK SVO_TRLLK LVS_LK_M LVS_TLN_M LVS_TUN_M N_ SVO_TRLT SVO_TRLT H LK_MH_O# N_ LKRQ# K H N_ IH_SYN# H MH_IH_SYN# H I RI RI N_ H VTT _PN- N R _R TSTN# N_ TSTN# R.R% H LVS_TLP_M LVS_TUP_M N_ lose to U (For MI) F N_ SVO TRLLK and TRLT H LVS_TUN_M LVS_TUN_M N_ can be shared or not?? lose to U (For MI) N_ H_LK N_ H_RST# RI N_ H_SI RI F N_ H_SO _R _R N_ H_SYN LVS_TUP_M LVS_TUP_M N_ F N_ Strapping onfigulation V M NTI_PM F F F F F F F V M I (efault=high) (efault=high) (efault=high) (efault=high) (efault=high) (efault=low) (efault=low) F SVO_TRL_T F V_R_M I PN MT Firmware MI* Low is Low is ynamic OT MI Lane Only SVO or will use TLS PI raphics PN nabled Reversal: Normal PI is PI only not reversed High Low Low MM model ITPM NL chiper suite with I Lane:RVRS Operation operational confidentiality PN PI only reversed Low Low Low SVO only not reversed SVO only reversed SVO and PI not reversed SVO and PI reversed High Low High Low High High High High Low Low High High N R LK/ TROL/OMPNSTI RSV LK F MI RPHIS VI PM M MIS H UM model SVO_TRLT default is low So,default SVO/iHMI/P disable F_ F_ F_ F_ R R R R _.KR.KR _.KR _.KR _PN _PN F_ F_ F_ R R R _.KR _.KR _.KR VRUN LVS PI-PRSS RPHIS TV V lose to U (For MI) NTI- (MI/V) Size ocument Number Rev ustom MS- MSI ORPORTI Tuesday, February, ate: Sheet of

7 M M M M Q M Q M Q M Q M M M M Q M Q M M Q M Q M Q M Q M M M M M Q M Q M Q M M QS M Q M Q M Q M Q M Q M Q M Q M M M QS# M Q M Q M Q M Q M M QS# M QS M QS M M M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M QS# M QS# M M M QS M Q M Q M Q M QS# M QS M QS M Q M Q M M QS M M M Q M Q M Q M QS# M M M Q M Q M Q M M QS# M Q M Q M Q M Q M Q M QS M Q M Q M Q M Q M QS# M Q M Q M Q M Q M Q M Q M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M M M M M M M M M M M M QS# M QS# M QS M QS# M QS M QS# M QS M QS M QS M QS# M QS# M QS M QS# M QS M QS# M QS M M M M M M M M M M M M M M M M M M S, M S, M S, M S#, M Q[:] M Q[:] M S, M S, M S, M [:], M QS[:] M QS#[:] M M[:] M W#, M RS#, M RS#, M [:], M QS#[:] M QS[:] M M[:] M S#, M W#, Size ocument Number Rev ate: Sheet of MS- NTI- (R) MSI ORPORTI ustom Tuesday, February, Size ocument Number Rev ate: Sheet of MS- NTI- (R) MSI ORPORTI ustom Tuesday, February, Size ocument Number Rev ate: Sheet of MS- NTI- (R) MSI ORPORTI ustom Tuesday, February, R SYSTM MMORY U NTI_PM R SYSTM MMORY U NTI_PM S_Q_ K S_Q_ H S_Q_ S_Q_ Y S_Q_ T S_Q_ R S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ F S_Q_ P S_Q_ S_Q_ S_Q_ F S_Q_ F S_Q_ S_Q_ F S_Q_ H S_Q_ S_Q_ H S_Q_ S_Q_ P S_Q_ S_Q_ H S_Q_ H S_Q_ S_Q_ H S_Q_ S_Q_ H S_Q_ F S_Q_ F S_Q_ S_Q_ J S_Q_ S_Q_ S_Q_ Y S_Q_ Y S_Q_ F S_Q_ F S_Q_ S_Q_ S_Q_ V S_Q_ U S_Q_ J S_Q_ R S_Q_ N S_Q_ Y S_Q_ V S_Q_ P S_Q_ R S_Q_ L S_Q_ L S_Q_ J S_Q_ H S_Q_ M S_Q_ M S_Q_ M S_Q_ H S_Q_ J S_Q_ P S_Q_ U S_Q_ U S_S_ S_S_ S_S_ S_S# S_M_ M S_M_ Y S_M_ S_M_ F S_M_ S_M_ S_M_ P S_M_ K S_QS_ L S_QS_ V S_QS_ S_QS_ S_QS_ H S_QS_ S_QS_ U S_QS_ N S_QS#_ L S_QS#_ V S_QS#_ H S_QS#_ H S_QS#_ S_QS#_ S_QS#_ T S_QS#_ N S_M_ V S_M_ S_M_ S_M_ W S_M_ Y S_M_ H S_M_ S_M_ U S_M_ W S_M_ S_M_ U S_M_ W S_M_ T S_M_ S_M_ U S_RS# U S_W# F R SYSTM MMORY U NTI_PM R SYSTM MMORY U NTI_PM S_Q_ J S_Q_ J S_Q_ U S_Q_ T S_Q_ N S_Q_ N S_Q_ U S_Q_ U S_Q_ V S_Q_ Y S_Q_ S_Q_ S_Q_ N S_Q_ V S_Q_ Y S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ T S_Q_ Y S_Q_ S_Q_ M S_Q_ V S_Q_ W S_Q_ S_Q_ U S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ J S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ V S_Q_ J S_Q_ T S_Q_ N S_Q_ U S_Q_ U S_Q_ T S_Q_ N S_Q_ M S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_ N S_S_ S_S_ S_S_ T S_S# S_M_ M S_M_ T S_M_ Y S_M_ U S_M_ S_M_ Y S_M_ T S_QS_ J S_QS_ T S_QS_ S_QS_ S_QS_ W S_QS_ S_QS_ U S_QS_ M S_M_ J S_QS#_ J S_QS#_ T S_QS#_ S_QS#_ S_QS#_ Y S_QS#_ S_QS#_ U S_QS#_ M S_M_ S_M_ S_M_ S_M_ S_M_ H S_M_ H S_M_ S_M_ H S_M_ S_M_ S_M_ S_M_ S_M_ F S_M_ W S_RS# S_W# Y S_M_ Y

8 U _VIMM () P _VM V NTF_ W UF V_SM_ N (.) V_SM_ V NTF_ V H V_SM_ V NTF_ W V_SM_ V NTF_ V F V_SM_ V NTF_ W V_SM_ V NTF_ V V_.U. V_SM_ V NTF_ W u.pso-.u..u V_ V_ V_SM_ V NTF_ V V_ V_SM_ V NTF_ W Y V_ Y V_SM_ V NTF_ V V V_ W V_SM_ V NTF_ M U V_ V V_SM_ V NTF_ L M V_ U V_SM_ V NTF_ K K V_ T V_SM_ V NTF_ W J R VF_OR V_ V_SM_ V NTF_ V V_ P V_SM_ V NTF_ U F V_ N V_SM_ V NTF_ M H V_SM_ V NTF_ K V_ V_SM_ V NTF_ W V_ F V_SM_ V NTF_ U V_SM_ V NTF_ M V_ Y H V_SM_ V NTF_ L u.pso-.u. UY V_ W V_ V_SM_ V NTF_ K V V_ F V_SM_ V NTF_ J U V_ V_SM_ V NTF_ H H V_ V_SM_ V NTF_ F V_ V_SM_ V NTF_ F V_ V_SM_ V NTF_ V_ Y V_SM_ V NTF_ J V_ W V_SM_ V NTF_ V_ V V_SM_ V NTF_ Y V_ U V_SM_ V NTF_ W V_ T V_SM_ V NTF_ V H R V_SM_ V NTF_ U V_ P V_SM_ V NTF_ M U. UY.U.U _UY V_ F V_ V NTF_ K V_ V_SM_/N V NTF_ H J V VM V_SM_/N V NTF_ H V_ V_SM_/N V NTF_ F F V_ V_SM_/N V NTF_ V_NTF_ M W V_SM_/N V NTF_ T V_ V_NTF_ L W V_SM_/N V NTF_ V_NTF_ K T V_SM_/N V NTF_ Y V_NTF_ J VF_OR V NTF_ W _VIMM V_NTF_ H V NTF_ V V_NTF_ (.) V NTF_ M / change to.v PSO V_NTF_ Y V V NTF_ L V_NTF_ V V NTF_ K V_NTF_ V V NTF_ J V V NTF_ H V_NTF_ Y V V NTF_ u.pso- U. V_NTF_ W PN V_NTF_ U V V NTF_ F V_NTF_ M V V NTF_ V_NTF_ L Y V V NTF_ V_NTF_ K V V NTF_ V_NTF_ H V V NTF_ / Stuff p for MI V_NTF_ V V NTF_ Y V_NTF_ F V V NTF_ W V_NTF_ J V V NTF_ V VF_OR V_NTF_ V V NTF_ U V_NTF_ V V_NTF_ V V_NTF_ Y V V_NTF_ W Y V V_NTF_ V H V V_NTF_ U F V V_NTF_ L V V_NTF_ K V V_NTF_ J V V_NTF_ H V V_NTF_ T V V_NTF_ T V V_NTF_ M V V_NTF_ L V V_NTF_ Y V V_NTF_ W J V V_NTF_ V H V V_NTF_ L V V_NTF_ K F V V_NTF_ L V V_NTF_ K V V_NTF_ K Y V V_NTF_ K V V V_NTF_ K U V N VSM_LF UY V M V U VSM_LF V V_SM_LF V UY T V V_SM_LF VSM_LF V_SM_LF M.U V_SM_LF V NTI_PM VSM_LF V_SM_LF Y.U. V_SM_LF M JN VSM_LF V_SM_LF.U. _NR VSM_LF.U J V SNS H VSS SNS VSM_LF.U POWR V SM V F V F NTF V SM LF V OR POWR V NTF JN _NR NTI_PM Feedback pin but if unused can be N?? MSI ORPORTI NTI- (POWR-) Size ocument Number Rev ustom MS- ate: Tuesday, February, Sheet of

9 VRUN_RT VRUN UH VTT L Lm (m) (m) VTT_ U VTT_ T.U.u V_RT VTT_ U V_RT VTT_ T.U..U..u..U VTT_ U u.-rh (m) VTT_ T V VTT_ U 有一顆 VTT 的大電容要靠近此區 VSS VTT_ T VTT_ U elete? _M_PLL VTT_ T VTT_ U (.m) F (Need check with power page if existed) _M_PLL V_PLL VTT_ T VTT_ U L _M_HPLL V_PLL VTT_ T VTT_ U (m) _M_MPLL V_HPLL VTT_ T Place close to N _VM _M_PLL VTT_ U (.m) VTT VRUN _VSUS_TLVS V_MPLL VTT_ T R L Um_ VTT_ V VTT_ U VFOL, change to uf (.m) J V_LVS VTT_ V VTT_ U (small size) J SSV- U..U VSS_LVS VTT_ T R _VRUN P VTT_ V VTT_ U (.m) V_P M_PLL _M_PPLL L Um_.U (m) _VM _VM V_P_PLL (.m) U..U (m) R V_SM_ P V_SM_ N V_SM_ R UY _UY.u. _U. UY V_SM_ POWR P _u. U. V_SM_ hange to ohm N V_SM_ T _VM _M_HPLL _VM V_SM_ R _VSUS_SM_LK _VIMM V_SM_ P R R R R V_SM_K V_SM_ L Um_ (m) R hange to ohm.u..u _.u. R% U..U.U P V_SM_K_ N _M_MPLL V_SM_K_ V_F_ P V_SM_K_ V_F_ N UY L Lm- V_SM_K_ V_F_ N V_SM_K_ M V_SM_K_NTF_ M V_SM_K_NTF_ M U..U V_SM_K_NTF_ L _VSUS_TLVS _VIMM V_SM_K_NTF_ V_SM_K_ F M V_SM_K_NTF_ V_SM_K_ H L L Um_ VRUN_RT V_SM_K_NTF_ V_SM_K_ M _VM _M_PPLL V_SM_K_NTF_ V_SM_K_ F L V_SM_K_NTF_ V_H change to N L Lm (m) (.m) P U. if HMI disable V_T_LVS K (Follow design guide p) JN _VRUN V_TV VRUN _VRUN V_TV V_HV NR (.m) V_HV_ R _R.U.U V_HV_ (m) R R _VM V_H (.) V_P_ V.U V_P_ U UY.U.u V_P_ V (m) V_P_ U M V_TV V_P_ U elete (uf) (.m) U. _.U.u. _VM _VRUN_Q L V_Q (.m) (m) V_MI_ H F _M_PPLL V_HPLL V_MI_ F (m) V_MI_ H _VRUN _VRUN_Q V_P_PLL V_MI_.U _VIMM(.m) _U..U L Lm M.U V_LVS_ L VTTLF V_LVS_ VTTLF VTTLF VTTLF L VTTLF VTTLF.U.U.u u.- NTI_PM.U.U.U RT PLL LVS P SM TV H LVS K TV/RT F SM K MI HV P VTT VTTLF NTI- (POWR-) Size ocument Number Rev ustom MS- MSI ORPORTI ate: Tuesday, February, Sheet of

10 Size ocument Number Rev ate: Sheet of MS- NTI- (VSS) MSI ORPORTI ustom Tuesday, February, Size ocument Number Rev ate: Sheet of MS- NTI- (VSS) MSI ORPORTI ustom Tuesday, February, Size ocument Number Rev ate: Sheet of MS- NTI- (VSS) MSI ORPORTI ustom Tuesday, February, Notice: If there is any layout import issue by updated ball name? _NR JN _NR JN VSS VSS NTF VSS S N UJ NTI_PM VSS VSS NTF VSS S N UJ NTI_PM VSS_ VSS_ W VSS_ U VSS_ P VSS_ N VSS_ H VSS_ F VSS_ VSS_ R VSS_ M VSS_ J VSS_ VSS_ VSS_ VSS_ W VSS_ T VSS_ J VSS_ VSS_ Y VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ W VSS_ T VSS_ R VSS_ M VSS_ H VSS_ VSS_ VSS_ U VSS_ N VSS_ N VSS_ K VSS_ VSS_ VSS_ VSS_ W VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ N VSS_ J VSS_ VSS_ N VSS_ L VSS_ VSS_ VSS_ F VSS_ V VSS_ T VSS_ M VSS_ VSS_ J VSS_ VSS_ VSS_ VSS_ Y VSS_ N VSS_ H VSS_ Y VSS_ N VSS_ VSS_ VSS_ VSS_ V VSS_ T VSS_ J VSS_ VSS_ VSS_ H VSS_ VSS_ VSS_ VSS_ M VSS_ N VSS_ VSS_ M VSS_ F VSS_ H VSS_ Y VSS_ L VSS_ VSS_ VSS_ Y VSS_ U VSS_ N VSS_ J VSS_ VSS_ VSS_ N VSS_ J VSS_ VSS_ VSS_ V VSS_ T VSS_ VSS_ M VSS_ M VSS_ VSS_ VSS_ H VSS_ VSS_ Y VSS_ L VSS_ J VSS_ H VSS_ F VSS_ VSS_ VSS_ V VSS_ L VSS_NTF_ F VSS_NTF_ VSS_NTF_ V VSS_NTF_ J VSS_NTF_ M VSS_NTF_ F VSS_NTF_ VSS_NTF_ U VSS_NTF_ U VSS_NTF_ L VSS_NTF_ V VSS_NTF_ VSS_NTF_ L VSS_NTF_ J VSS_NTF_ VSS_NTF_ U VSS_S_ H VSS_S_ H VSS_S_ VSS_S_ VSS_S_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ F N_ N_ N_ VSS_ R VSS_ P VSS_ VSS_ R VSS_ U VSS_ P VSS_ F VSS_ W VSS_ VSS_ F VSS_ H VSS_ J VSS_ VSS_ VSS_ Y VSS_ M VSS_ K VSS_ M VSS_ VSS_ P VSS_ H VSS_ VSS_ V VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_ L VSS_ J N NR JN _NR JN _NR JN _NR JN _NR JN _NR JN _NR JN _NR JN VSS UI NTI_PM VSS UI NTI_PM VSS_ U VSS_ VSS_ R VSS_ L VSS_ VSS_ W VSS_ N VSS_ J VSS_ F VSS_ VSS_ VSS_ Y VSS_ T VSS_ N VSS_ L VSS_ VSS_ VSS_ VSS_ V VSS_ R VSS_ M VSS_ V VSS_ R VSS_ P VSS_ H VSS_ F VSS_ F VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ F VSS_ VSS_ V VSS_ U VSS_ M VSS_ J VSS_ VSS_ VSS_ Y VSS_ T VSS_ N VSS_ J VSS_ VSS_ N VSS_ L VSS_ VSS_ U VSS_ M VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ VSS_ VSS_ VSS_ VSS_ V VSS_ N VSS_ H VSS_ VSS_ T VSS_ M VSS_ J VSS_ VSS_ N VSS_ L VSS_ VSS_ H VSS_ VSS_ VSS_ U VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ J VSS_ F VSS_ VSS_ VSS_ M VSS_ VSS_ P VSS_ L VSS_ J VSS_ F VSS_ VSS_ H VSS_ VSS_ Y VSS_ U VSS_ T VSS_ F VSS_ M VSS_ J VSS_ F VSS_ VSS_ W VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ V VSS_ R VSS_ L VSS_ H VSS_ VSS_ P VSS_ L VSS_ H VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ N VSS_ T VSS_ N VSS_ K VSS_ H VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ V VSS_ T VSS_ R VSS_ J VSS_ VSS_ VSS_ VSS_ Y VSS_ P VSS_ K VSS_ H VSS_ F VSS_ VSS_ F VSS_ H VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ H VSS_ VSS_ VSS_ V VSS_ R VSS_ J VSS_ VSS_ Y VSS_ N VSS_ L VSS_ J VSS_ VSS_ VSS_ F VSS_ F VSS_ VSS_ W VSS_ T VSS_ N VSS_ J VSS_ H VSS_ VSS_ VSS_ U VSS_ T VSS_ H VSS_ VSS_ L VSS_ Y VSS_ VSS_ VSS_ VSS_ VSS_ Y VSS_ J VSS_ F VSS_ R VSS_ K VSS_ J VSS_ F VSS_ H VSS_ Y VSS_ K VSS_

11 M Q[:] IMM M [:], M Q M IMM M Q Q M M Q Q M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M VM V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q /P M V VSS M Q Q M V VSS M Q Q M V VSS.U.Y M Q Q.U M VSS M Q Q _VIMM VSP VSS M Q Q VSS M S, M Q Q _ N VSS M Q Q N VSS R _R M S, M Q Q PM_TTS# N VSS R M S, M Q Q N VSS KR% M_S#, M Q Q S# SMR_VRF NTST VSS M_S#, M Q Q S# N VSS M_LK_R M Q Q K SMR_VRF N VSS M_LK_R# M Q Q K# VRF VSS M_LK_R M Q Q K VSS M_LK_R# M Q Q K# N VSS M_K, M Q Q K R N VSS M_K, M Q Q K KR%.U.Y VSS.U M S#, M Q Q S# _.U VSS VSS M RS#, M Q Q RS# VSS VSS M W#, M Q Q W# S_S VSS VSS M Q Q S R KR S_S VSS VSS R KR M Q Q S VSS VSS SM_LK_M,, as close as SO-IMM Trace : mils M Q Q SL VSS VSS SM_T_M,, M Q Q S VSS VSS M Q Q VSS VSS M_OT, M Q Q OT VSS VSS M_OT, M Q Q OT VSS VSS M M[:] M Q Q M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M R-Reverse M Q Q M M M M Q Q M M M M Q Q M M QS[:] M Q Q M QS Layout note: Place capacitors between M Q Q QS M QS _VIMM and near R connector if possible. M Q Q QS M QS M Q Q QS M QS M Q Q QS M QS M Q Q QS M QS M Q Q QS M QS M Q Q QS M QS.U.U.U M QS#[:] M Q Q QS.U M QS# M Q Q QS# M QS# M Q Q QS# M QS# M Q Q QS# M QS# M Q Q QS# M QS# M Q Q QS# M QS# M Q Q QS# M QS# _VIMM M Q Q QS# M QS# Q QS# _VIMM R-Reverse.U.Y.U.Y.U.Y.U.Y.U.Y _u.-rh placed close to IMM MSI ORPORTI R SOIMM Size ocument Number Rev ustom MS- ate: Tuesday, February, Sheet of

12 M Q[:] M Q M VIMM M Q Q M M Q Q M M Q Q IMM M M Q Q M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M VM V VSS M Q Q /P M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M V VSS M Q Q M Q Q V VSS M S, M Q Q _.U.Y.U VSS VSP VSS M Q Q VSS M S, M Q Q N VSS M S, M Q Q M_S#, M Q Q S# R _R N VSS PM_TTS# N VSS M_S#, M Q Q S# N VSS M_LK_R M Q Q K SMR_VRF NTST VSS M_LK_R# M Q Q K# N VSS M_LK_R M Q Q K SMR_VRF N VSS M_LK_R# M Q Q K# VRF VSS M_K, M Q Q K VSS M_K, M Q Q K M S#, M Q Q S# N VSS M RS#, M Q Q RS#.U.Y.U N VSS VM VSS M W#, M Q Q W# S_S M Q Q S R KR VSS VSS S_S M Q Q S R KR VSS VSS VSS VSS SM_LK_M,, M Q Q SL VSS VSS SM_T_M,, as close as SO-IMM Trace : mils M Q Q S VSS VSS M Q Q VSS VSS M_OT, M Q Q OT VSS VSS M_OT, M Q Q OT VSS VSS M M[:] M Q Q M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M VSS VSS M Q Q M M M M Q Q M R-Reverse_H M QS[:] M Q Q M QS M Q Q QS M QS Layout note: Place capacitors between M Q Q QS M QS and near R connector if possible. M Q Q QS M QS _VIMM M Q Q QS M QS M Q Q QS M QS M Q Q QS M QS M Q Q QS M QS M QS#[:] M Q Q QS M QS# M Q Q QS# M QS# M Q Q QS#.U.U.U.U M QS# M Q Q QS# M QS# M Q Q QS# M QS# M Q Q QS# M QS# _VIMM M Q Q QS# M QS# M Q Q QS# M QS# Q QS# R-Reverse_H _u.-rh.u.y.u.y.u.y.u.y.u.y IMM M [:], R SOIMM Size ocument Number Rev ustom MS- MSI ORPORTI ate: Tuesday, February, Sheet of

13 M [:] M [:], SMR_VTRM M [:] RN RN M [:], M RS# M RS#, M RS# M RS#, M_S# M_S#, M_S# M_S#, M_OT M, M_OT M M_OT M_OT, SMR_VTRM RN RN PR-R PR-R M M RN RN M M M_OT M, M_OT M M M_S# M, M_S# M M S M S M M S,, M S M S# M_K, M S# M_K, PR-R PR-R RN RN PR-R PR-R M M RN RN M M M M S M S, M M M M W# M W#, M S M M M S#, M S M S#, M_K M_S#, M_K M_S#, PR-R PR-R RN RN PR-R PR-R M M S M S, M M M W# R R R R M_K, M W# M_K, M_K M, M_K M S M M M_OT, M S R R R R M_OT, PR-R PR-R M R R R R M SMR_VTRM Layout note: Place one cap close to every pullup resistors terminated to SMR_VTRN. SMR_VTRM.U.U.U.U.U.U.U.U.U.U.U.U.U SMR_VTRM SMR_VTRM.U.U.U.U.U.U.U.U.U.U.U.U.U SMR_VTRM If mount uf, other Ps can be cost down? UY UY R TRMINTI Size ocument Number Rev ustom MS- MSI ORPORTI ate: Tuesday, February, Sheet of

14 VLKN / Wait for new part number PM_STPPI#/PM_STPPU# pin change R _KR FRRUN# U VLKN R KR LK_PU PUT_L*** R R RLTH** LK_PU_LK LK_PU_# R R LK_PU_LK# R KR LP LK_R PU_L*** LK_PWR VTT_P/WOL_STOP# LK_PU PUT_LF*** R R LK_MH_LK,, SM_LK_M R R LK_PU# R R LK_MH_LK# PLK_R_R,, SM_T_M R R PU_LF*** R _KR SLK _FSO _FSO R R ST LK_OT_R R R RFLK _FSO _FSO R R O_** OTT_LR/PIeT_LR LK_OT#_R R R RFLK# R KR SL O_** OT_LR/PIe_LR VLKN FRRUN# LK_PI_R RFSSLK LP LK_R PIeT_LR R R MHz_F_x/PLKRQ#/Freerun* LK_PI#_R RFSSLK# FS MHz_F/PLKRQ#/SL_STOP** PIe_LR R R L R R PI_SL LK_US R KR VM R R FS FSL/US_MHz LK_RF_IH FSL/RF_x PIeT_LR/PLKRQ# TP R R NWR_LKRQ- R _KR PLK_R_R LK_SIO_ PIe_LR/PLKRQ# R _R% L-_ PI_SL SL_#/_MHz* PM_STPPI#_R PM_STPPI# FS PM_STPPI# *PI_STOP#/PIeT_LR R R R KR R _R PM_STPPU#_R R R PM_STPPU# PM_STPPU# R _R PILK *PU_STOP#/PIe_LR R KR RST# PLK_R_R PILK / not stuff FS FS/PILK_x** PIeT_LR LP_SIO_LK R R RST# FSL/PILK_x PIe_LR VRUN leakage current issue SL SLRST/RST#/PILK** SL/PILK** PIeT_LR/PLKRQ# TP PIe_LR/PLKRQ# TP VPI LK_NW_R_R R R PIeT_LR LK_NW_R PIN, FUNTI PIN STRP VLKN L L-_ VPI LK_NW_R#_R R R VPI PIe_LR LK_NW_R- VI/O PU/PI STOP LK_PI_IH_R R R VI/O PIeT_LR LK_PI_IH LK_PI_IH#_R R R VPU PIe_LR LK_PI_IH# PILK V V VLKN L L-_ V PIeT_LR PIe_LR VRF PIN, FUNTI PIN STRP L LK_PI_PLL_R R R VST PIeT_LR LK_PI_PLL VLKN LK_PI_PLL#_R R R VMHz PIe_LR LK_PI_PLL# M PIe PU_SL PU_SL MH_SL MH_SL PU_SL PU_SL PU_SL PU_SL FS FS VLKN LK_MINI_PI_R LK_MINI_PI#_R LK_MINI_PI_R LK_MINI_PI#_R LK_PI_ST_R LK_PI_ST#_R RN PR-R PN PLK_R PLK_R_R LP_U FS LP LK LK_PIF_IH SL ST_LKN R R R R R R / etele.vm LO,because only save m ifferential power still use.v VLKN S KR KR R _MR Q _N.UY R _KR.UY.uY L UY L-_ / dd, L~ by vendor.uy.uy L-_ UY.UY.UY.UY.UY / Need to build filter bead for LK_Vs? / Modify to R by MI / dded for IT pin function conflicted / elete beacause cannot use clock signal to switch.uy.uy V N NPI NPI N N N N N N N N N P / lock generator change to SL[] L L PU Table SL[] H H STLKT_LR STLK_LR SL[] H L PIeT_LR PIe_LR PIeT_LR PIe_LR ISLPRS FS Freq (MHz) MHz MHz TL_IN TL_OUT Y.MHZP_S-RH R R R R R R PLK_R LK_PIF_IH LP_U LP LK LK_US LK_RF_IH LK_SIO_ LP_SIO_LK R R R R R R MI PN LK_MINI_PI LK_MINI_PI# LK_MINI_PI LK_MINI_PI# LK_PI_ST LK_PI_ST# / stuff For IH PI clock timing match PN PN PN PN PN PN PN PN.UY UY LK_ST_O# S LP LK_R Q _P-FNP_SOT--RH R _R% MSI ORPORTI LK N [ISLPRS] Size ocument Number Rev ustom MS- ate: Tuesday, February, Sheet of

15 VRUN VRUN For MI / OK_N# Low :Yn to n High :Yn to n OK_N# VRUN R KR V_R_M V M V M V_HSYN_M V_VSYN_M U V SL V V Ohm V Y Y I Y I Y I Y I I N N I N I N I I I PIVQ_QSOP VRUN Ohm V_R V_ V_.U.U.U OK_R OK_ R R OK_ OK_HS /.KR.KR OK_VS Ohm Ohm L.um LR L.um LRN L.um LLU HSYN VSYN R R R R% R% R% VRUN.U S-SWS_SO-RH RTV _PN _PN _PN _PN- _PN- _PN- PN- PN- PN- PN- PN- PN- / PN- RTV.U HSYN VSYN N--SUF_blue- N-F- vga_dsubpf R _R _R / by MI V_R_M V M V M _.PN _.PN _.PN R.KR Q N-SSLT_SOT--RH V_LK_M S V_T_M R.KR Q N-SSLT_SOT--RH S U LR LRN LLU VSYN HSYN RTV / Stuff,,, For MI _Z-PNMR-MSOP Rds(on)=mohm VRUN Id=. R MR LVS_VN_M R KR S LVS_VN# R KR Q N SOTS_T Q IRLMLPF_SOT S.U /LVS_VN# U.-.U LVS_VN# Q N SOTS_T / V_L R R S LI- R-J h.l LVS_TLN# LVS_TLP# LVS_TLN# LVS_TLP# LVS_TLN# LVS_TLP# LVS_TLLKN# LVS_TLLKP# h.u LVS_TULKN# LVS_TULKP# LVS_TUN# LVS_TUP# LVS_LK_M LVS_T_M LVS_TUN# LVS_TUP# LVS_TUN# LVS_TUP# LVS_LK_M LVS_T_M VRUN.U PWR_INVRTR LVS_TULKP_M LVS_TULKN_M LVS_TUP_M LVS_TUN_M For MI LVS_TULKP_M L M-L--M LVS_TULKN_M LVS_TUP_M L M-L--M LVS_TUN_M R R R R R _R LVS_TULKP# R _R LVS_TULKN# _R _R LVS_TUP# R _R LVS_TUN# _R _R R LVS_TLP# R _R LVS_TLN# R R LVS_TLP# R _R LVS_TLN# R R _R LVS_TLP_M L M-L--M LVS_TLN_M _R _R LVS_TLP_M L M-L--M LVS_TLN_M _R _R LVS_TLP_M LVS_TLN_M LVS_TLP_M LVS_TLN_M LVS_TUP_M LVS_TUP_M LVS_TUP# LVS_TLLKP# LVS_TLLKP_M LVS_TLLKP_M _L L_M R _R LI# R KR VRUN L- R R R--J U SP_S.U R R.U LI- R-J LVS_P <N NM> N--H VRUN LVS_TUN_M LVS_TUP_M L M-L--M LVS_TUN_M LVS_TUP_M L R R R _R LVS_TUN# _R _R LVS_TUP# R R _R LVS_TLLKN# R R LVS_TLP# R L M-L--M LVS_TLLKN_M LVS_TLLKN_M _R _R LVS_TLP_M LVS_TLP_M.U U V N VOUT PI-TRL_SOT--RH I-- VRUN PWR_SR R KR LI# LI# P L L-_.U PWR_INVRTR.U R.KR LVS_T_M LVS_LK_M R.KR LVS_TUN_M M-L--M LVS_TUN_M / Stuff M for MI S tested pass R _R LVS_TUN# _R _R MSI ORPORTI V, LVS,L,TV,US SW Size ocument Number Rev ustom MS- L M-L--M LVS_TLN# LVS_TLN_M LVS_TLN_M R _R Tuesday, February, ate: Sheet of

16 VTT H_PSLP# R _R VLW H_PRSTP# R _R H_FRR# R R RTV PM_THRMTRIP# R R / Modify T R KR- RT issue _P O_H_ITLK R KR RT_P UY R MR SM_INTRUR# RTV R UY JRT HHS-.PITH-RH R RTRST _R KR- UY R RTV RT RT RTRST# SRTRST# SM_INTRUR# IH_INTVRMN R R M_H_IT_LK LN_LK LN_LK T N H_T M# J H_M# LN_RSTSYN _VRUN VSUS LN_RSTSYN PRSTP# PRSTP# J JN _NR PSLP# H_PRSTP#,, LN_R F LN_R PSLP# JN _NR H_PSLP# LN_R PN PN LN_R FRR# LN_R LN_R FRR# J R R H_FRR# R R LN_T.R% KR LN_T PUPWR H_PWR LN_T R R LN_T O_H_SYN LN_T LN_T INN# F H_INN# R R INIT# M_H_SYN JN _NR LN_OK#/PIO INIT# H_INIT# INTR H_INTR KRST# LN_OMPI LN_OMPI RIN# L LN_OMPO H_NMI H_IT_LK_IH NMI F F SMI# H_SYN_IH H_IT_LK SMI# F JN _NR _PN _PN H_SMI# H H_SYN H_RST#_IH STPLK# H H_STPLK# H_RST# THRMTRIP# THRMTRIP# R.R% PM_THRMTRIP#, O_H_SIN F R R H_SIN TP TP O_H_RST# H_SIN TP H_SIN TP H R R TP H_SIN M_H_RST# H_SIN STRN_ STRN H_SOUT_IH STRN H.U STRP_ H_SOUT STRP J STTN_ STRP PIO_ STTN.U R KR STTP_ PIO R R H_OK_RST# H_OK_N#/PIO STTP F O_H_SOUT TP.U H_OK_RST#/PIO STTN R R STRN H M_H_SOUT ST_TIV# STL# STRP J.U STTP.U STRN_ STTN STRN J STRP_ STRN STTP F H Place ap lose to onnector.u STTN_ STRP STRP F STTP_ STTN ST_LKN H _PN _PN.U STTP ST_LKP J STTN H.U STRN STRIS# J STTP J STRP STRIS H Place ap lose to onnector STTN F STTP LK_PI_ST# LK_PI_ST IHM RV. STRIS ST_RN ST_RN pn R ST_RP ST_TN ST_TP pn Y.KHZ.P_S-RH- KR% R MR% ST_RP ST_TN ST_TP U RT RT RTRST# F SRTRST# INTRUR# INTVRMN LN_SLP RT LP LN / LN PU IH ST FWH/L K FWH/L K FWH/L L FWH/L K FWH/LFRM# K LRQ# J LRQ#/PIO J L L L L LRQ# Trace <." TP L, L, L, L, LP_FRM#, L_LRQ#, R.R% VRUN PIO_ OR hain ntrance Strap R R IH_TP H_SOUT escription _KR _KR RSV H_SOUT_IH nter OR hain Normal Operation(efault) Set PI port config bit / reserved MSI ORPORTI IHM- (PU/I/zalia) Size ocument Number Rev ustom MS- ate: Tuesday, February, Sheet of

17 place ap close to IH within mils U PI_NWR_RN N PRN MIRN V MI_RN PI_NWR_RP N MI_RP.U PTN PRP MIRP V PI_NWR_TN P MI_TN PI_[:].U PTP PTN MITN U PI_NWR_TP P PTP MITP U MI_TP U L PI_ PI_RQ# PRN MIRN Y MI_RN PI_ RQ# F PI_RQ# L PI_NT# PRP MIRP Y MI_RP PI_ PI NT# PI_NT# M PI_RQ# PTN MITN W MI_TN PI_ RQ#/PIO M NT# TP PTP MITP W MI_TP PI_ NT#/PIO PI_RQ# PI_ RQ#/PIO F NT# PI_MINI_RN J TP PRN MIRN MI_RN PI_ NT#/PIO F PI_RQ# PI_MINI_RP J MI_RP.U PTN PRP MIRP PI_ RQ#/PIO NT# PI_MINI_TN K MI_TN.U PTP PTN MITN PI_ NT#/PIO F TP PI_MINI_TP K PTP MITP MI_TP PI_ PI_# PI_# PI_ /# PI_# PI_MINI_RN PRN MIRN MI_RN PI_# _VRUN PI_ /# PI_# PI_MINI_RP MI_RP PI_#.U PTN PRP MIRP F PI_ /# PI_# PI_MINI_TN H MI_TN F PI_# PTP PI_ /#.U PTN MITN PI_MINI_TP H PTP MITP MI_TP PI_ PI_IRY# PI_IRY# R PI_ IRY# PI_PR PRN MI_LKN T LK_PI_IH# PI_PR.R% PI_ PR PRP MI_LKP T LK_PI_IH F R_RST# PI_ PIRST# R F PI_VSL# PTN PI_VSL# PI_ VSL# F PI_PRR# PTP MI_ZOMP F MI_ZOMP PI_ PRR# PI_LOK# MI_IROMP F PI_ PLOK# PI_SRR# PI_LN_RN PRN/LN_RN F PI_ SRR# J PI_STOP# PI_LN_RP USPN PI_STOP# PTN PI_ STOP#.U PRP/LN_RP USPN PI_TRY# PI_LN_TN USPP F PI_TRY#.U PTP PTN/LN_TN USPP PI_ TRY# F PI_FRM# PI_LN_TP PTP/LN_TP USPN USPN Trace within F PI_FRM# PI_ FRM# USPP." with R R SPILK USPP PI_ PLT_RST# SPI_LK USPN SPI_S# mils PI_ PLTRST# R R SPI_LK USPN LK_PIF_IH SPI_S# USPP H LK_PIF_IH R R SPI_S# SPI_S# USPP PI_ PILK PI_PM# SPI_S# F SPI_S#/PIO/LPIO USPN USPN PI_PM# PI_ PM# R USPP R R SPI_MOSI USPP PI_ SPI_SI OK_USPN H PM reserved ohm?? SPI_MOSI USPN PI_ SPI_SO SPI_MISO USPP OK_USPP PI_ USPN H O# USPN N USPP VM_WOL O# O#/PIO USPP N USPN Interrupt I/F O# O#/PIO USPN INT_PIRQ# INT_PIRQ# US W N USPP INT_PIRQ# J R KR O# O#/PIO USPP W INT_PIRQ# PIRQ# PIRQ#/PIO H P INT_PIRQF# USPN O# O#/PIO USPN Y INT_PIRQ# PIRQ# PIRQF#/PIO K M INT_PIRQ# USPP J O# O#/PIO USPP Y INT_PIRQ# PIRQ# PIRQ#/PIO F N INT_PIRQH# USPN O# O#/PIO USPN W PIRQ# PIRQH#/PIO M USPP O# O#/PIO USPP W M IHM RV. USPN O# O#/PIO USPN V N USPP O# O#/PIO USPP V N USPN SPI_LK O# O#/PIO USPN U P USPP / US swap O# O#/PIO USPP U P O#/PIO USPN U I USPP U _PN USRIS USRIS USRIS# lose to R R.R% VRUN IHM RV. Trace <." PI-xpress SPI irect Media Interface VRUN RN PR-.KR PI_PRR# PI_LOK# PI_IRY# INT_PIRQ# RN PR-.KR INT_PIRQ# RN PR-.KR INT_PIRQ# INT_PIRQF# PI_RQ# VSUS PI_SRR# INT_PIRQH# INT_PIRQ#.U INT_PIRQ# RN PR-.KR PI_STOP# RN PR-.KR PI_VSL# INT_PIRQ# PI_FRM# VSUS PI_TRY# PI_RQ# U RN PR-R RN PR-KR R.KR PI_RQ# SP_S MINIPI_RST# O# R.KR PI_RQ# MINIPI_RST# O# NWR_RST# O# N_RST# O# PLT_RST# / R not stuff R R R _R LP_RST#, SVO_RST# RN PR-KR O# oot IOS Strap O# PI_NT# O# O# PI NT# SPI_S# oot IOS Location SPI_S# NT# and SPI_S# have RN PR-KR O# a weak internal pull up O# SPI (efault) O# O# R R PI _KR KR VSUS hange to PR type? LP IHM- (PI/US/PI/MI) Size ocument Number Rev MS- MSI ORPORTI ate: Tuesday, February, Sheet of

18 VSUS RN PR-KR SMLINK SMLINK SMLRT# SM_LINK_LRT# R KR PM_SYS_RST R.KR SUS_SMT VRUN RN PR-KR STP STP STP STP R.KR SUS_SMLK R KR PM_RI# U SUS_SMLK STP PI_WK# pull up K ohm?? R KR PM_T# SUS_SMT SMLK STP/PIO H STP SM_LINK_LRT# SMT STP/PIO F STP PI_WK# SMLINK STP/PIO R KR LINKLRT#/PIO/LPIO STP VM SMLINK SMLINK STP/PIO R _KR PM_PWRTN# SMLINK PM_RI# LK H LK_RF_IH F SUSPWRK LK F LK_US R KR RI# LPP# S_PIO LPP# R TP R KR R PM_SYS_RST SUS_STT#/LPP# SUSLK P R _KR _KR SYS_RST# SLP_S# JN _NR SLP_S# SLP_S# PM_SLP_S#,,, PM_SYN# M PMSYN#/PIO SLP_S# JN _NR PM_SLP_S# TP PM_SLP_S#, VRUN SMLRT# SLP_S# JN _NR SMLRT#/PIO R KR LK_ST_O# PM_STPPI# STP_PI#_R S_STT#/PIO PM_S_STT# JN _NR STP_PU#_R STP_PI# PWROK_S PM_SYN# PM_STPPU# JN _NR STP_PU# PWROK IMVP_PWR,, R _KR P_LKRUN# PRSLPVR S_PIO LKRUN# connect to??, P_LKRUN# L LKRUN# PRSLPVR/PIO M JN _NR R _KR PM_PRSLPVR, PM_T#, PI_WK# PM_THRM# WK# T# R KR, SIRQ M PM_THRM# SRIRQ J PM_PWRTN# PM_PWRTN# R KR SIRQ THRM# PWRTN# R VR_PWR_LKN LN_RST# R _R LNRST# P_LKRUN# VRMPWR LN_RST# R KR TP TP RSM_RST# RSMRST#, IMVP_PWR RSMRST# R R R KR TP KSMI# TP S_PIO PIO K_PWR R LK_PWR H PIO R _R IMVP_PWR IMVP_PWR# pull low K ohm?? KSI# TP PIO LPWROK R PIO MPWROK, VRUN S_PIO LN_PHY_PWR_TRL/PIO SLP_M# PM_SLP_M#,, TP S_PIO NRY_TT/PIO S_L_LK PIO L_LK F JN _NR L_LK U TP K L_LK S_PIO PIO L_LK TP F TP S_PIO PIO J S_L_T JN _NR L_T VR_PWR_LKN TP S_PIO SLOK/PIO L_T F VR_PWR_LKN# L_T TP S_PIO PIO L_T PIO L_VRF_IH LK_ST_O# L M_I STLKRQ#/PIO L_VRF NZ L_VRF_IH M_I SLO/PIO L_VRF R STOUT/PIO F S_L_RST# STOUT/PIO L_RST# F JN _NR L_RST# KR H L_RST# LPIO PIO L_RST# PIO/LPIO S_PIO VSUS MM_L/PIO SPKR M MH_SYN# SPKR PIO/SUS_PWR_K JN _NR SUSPWRK MH_IH_SYN# J _PRSNT TP MH_SYN# PIO/_PRSNT TP WOL_N/PIO TP LN_WOL_N, H R TP TP J LN_WOL_N need to pull high or low?? KR R TP TP J _KR TP IHM RV. The Management ngine Firmware uses the LPIO LPIO pin on the IHM to indicate VRUN R Physical Presence to the platform when pulled high. VSUS ndree.. _KR R _KR R KR S_PIO SM ST PIO locks SYS PIO Power MT MIS PIO ontroller Link VM SMLINK SMLINK R R _R _R TLK_M, TT_M, U R _KR LN_WOL_N R _KR For IOS recovery To Neward, Miniard R.KR VRUN Q N-SSLT_SOT--RH VSUS VM_WOL VM R _KR M_I R _KR VM M_I, SUS_SMLK S R _KR R _KR SM_LK_M,, R R R.KR% _.KR% _.KR% VM To R-SOIMM, LK en. R.KR% L_VRF_IH ndree.. L_VRF_IH M_I => High : MT Mode Low : Non MT Mode, SUS_SMT R.KR Q N-SSLT_SOT--RH S SM_T_M,, R R%.U R.U R% / hange WLN power to SUS / R change to KR For LN_RST# timing delay VSUS S-RV-_SO VSUS VM_WOL U U NWZ_S LN_RST# R R R KR NWZ_S U MSI ORPORTI IHM- (SM US/PIO) Size ocument Number Rev ustom MS- Tuesday, February, ate: Sheet of

19 VRF_SUS _VSTPLL VMI VMIPLL VSUS VSUS VSUS VL_ VL_ VSUS VRF VL_ VL_ VRUN _VRUN RTV VRUN VRUN VSUS VSUS VRUN _VRUN VM_WOL _VRUN VTT VTT _VRUN VSUS VM_WOL VRUN VTT _VRUN _VRUN VSUS Size ocument Number Rev ate: Sheet of MS- IHM- (POWR/N) MSI ORPORTI Tuesday, February, Size ocument Number Rev ate: Sheet of MS- IHM- (POWR/N) MSI ORPORTI Tuesday, February, Size ocument Number Rev ate: Sheet of MS- IHM- (POWR/N) MSI ORPORTI Tuesday, February, uh inductor (m) (m) (m) (m) (.) (m) (m) (.) (m) (m) (m) (m) (m) (.) (.) (m) (m) (m) (m) (m) (.) (m) elete L for Layout / hange to stuff uf / Stuff by MI / Stuff by MI.U.U.U.U.U.U.U.U.U.U L Um_ L Um_.U.U.U.Y.U.Y UY UY UY UY.U.U R R R R.U.U.U.U.U.Y.U.Y U. U. S-RV-_SO S-RV-_SO.U.U.U.U L um_-rh L um_-rh UY UY.U.U.U.U.U.U.U.U.U.U.u..u. U. U..u..u. U IHM RV. U IHM RV. VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] F VSS[] F VSS[] F VSS[] H VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] F VSS[] F VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] VSS[] U VSS[] U VSS[] U VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] H VSS_NTF[] H VSS_NTF[] J VSS_NTF[] J VSS_NTF[] J VSS_NTF[] J VSS_NTF[] VSS_NTF[] VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] VSS[] H VSS[] F VSS[] VSS[].U.U _.U _.U TP TP S-RV-_SO S-RV-_SO L Um_ L Um_.U.U TP TP _UY _UY R R R R.U.U.U..U..U.U TP TP UY UY.U.U.U.U.U.U _NR JN _NR JN UY UY OR VP T R US OR PI LN POWR VP_OR VPSUS VPUS UF IHM RV. OR VP T R US OR PI LN POWR VP_OR VPSUS VPUS UF IHM RV. VRF VRF_SUS V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] F V [] V [] H V [] H V [] J V [] J V [] K V [] K V [] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [] P V [] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] U V_[] VMIPLL R V [] V [] V [] V [] V [] F VSTPLL J V_[] J V [] V [] VUSPLL J VLN_[] VLN_[] V_[] V_[] V_[] V_[] V_[] V_[] F V_[] L V_[] L V_[] L V_[] L V_[] L V_[] L V_[] M V_[] M V_[] P V_[] P V_[] T V_[] T V_[] U V_[] U VLN_[] VLN_[] VH J VSUSH J V_PU_IO[] V_PU_IO[] V_[] F V_[] V_[] V_[] J V_[] J V_[] K VRT VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] T VSUS_[] T VSUS_[] T VSUS_[] T VSUS_[] T VSUS_[] T VSUS_[] U VSUS_[] U VSUS_[] V VSUS_[] V VSUS_[] W VSUS_[] W V [] VSUS_[] VSUS_[] F V [] V [] V [] V [] V [] VSUS_[] F V_[] V [] V_[] V V_[] V V_[] V V_[] V V_[] V V_[] V VLN_[] VLN_[] VLN_[] VLN_[] VLN_ VLNPLL V_[] VSUS_[] Y VSUS_[] VSUS_[] F V_MI[] Y V_MI[] W VL_ VL_[] VL_[] VL_ V [] W V [] V V [] U V [] W V [] U V [] V V [] K V [] Y V [] Y V [] V [] H V [] J V [] V [] F VSUS_[] Y V_[] F V_[] V_[] V_[] V [] V [] V [] V [] V [] V [] J V [] H V [] V [] V [] V [] VSUS_[] T U.SP-LF U.SP-LF.u.u.U.U.U.U.U.U UY UY U. U.

20 , VRUN L_LRQ# LP_U VSUS KRST# VRUN VRUN _PRSNT KRST# LP_FRM# L L L L L_LRQ# LP_U SIRQ LP_RST# FWH_I LP ebug interface / Stuff for O pin R KR RN PR-KR RN R PR-KR _KR KSMI# KSI# KRST# H_T RSMRST# NH PR_H NH_P hange to PR type VLW R HHS_white-RH N--M _ lose to Pin OK_PS_LK OK_PS_T OK_PS_LK OK_PS_T TP_LK TP_T R _S-SWS_SO-RH.UY S-RV-_SO K_RST# _UY,,,,,,, _RST# K builds in power on reset Power on :.~.V Reset Power off :.~.V Reset hange to PR type? R KR R KR,,,,,,, sk N ric what's the LKRUN#? VRUN _IN# T_IN# T_WLN_K# PM_SLP_S# MIL_K# TP LI# SUSPWROK _PRSNT SUSPWRK L_PI# PM_SLP_M# PWR_SW_K# _TL L_O# I_K# PM_SLP_S# _SPILK O_K# LP_RST# SIRQ LP_FRM# L L L L LP LK TP RN PR-KR _LKRUN# K_RST# _T K_SI# KIN KIN KIN KIN KIN KIN KIN KIN KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT SRH/MR_K# LLSYSP K_SMI# K_PWRT# /PM_SLP_S# R _R R R _PN For MI / U N N N N N PIO/LRST# SRIRQ LFRM# L L LP L L LLK PIO/LKRUN# PIO/KRST# PIO/ PIO/SI# RST# PIO/KSI/ISP_R PIO/KSI PIO/KSI PIO/KSI PIO/KSI PIO/KSI PIO/KSI PIO/KSI PIO/KSO/TP_TST PIO/KSO/TP_PLL PIO/KSO PIO/KSO/ISP_N# PIO/KSO PIO/KSO K PIO/KSO PIO/KSO PIO/KSO PIO/KSO PIO/KSO PIO/KSO PIO/KSO PIO/KSO PIO/KSO PIOF/KSO/ISP_T PIO/KSO PIO/KSO PIO/PSLK/P_LK PIO/PST/P_T PIO/PSLK PIO/PST PIO/PSLK PS I/F PIOF/PST PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIOF PIO PIO PIO PIO/SPI_LK PIO PIO/IR_RL_T IR PIO/IR_R / dd For bad issue PIO POWR & N -US SM-US PWM / / LOKS N- UY V N PIO/SPI_SL# PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PO PO PO PIO/ PI PI PI PI PI PI PI PI PIO/_T PIO/_R PIO/SL PIO/S PIO/SL PIO/S PIOF/PWM PIO/PWM PIO/FNPWM PIO/FNPWM PIO/FNF PIO/FNF PO/ PO/ PO/ POF/ PI/ PI/ PI/ PI/ PI/ PI/ V V V V V V LKI LKO LKO_N VRUN R#/SPI_I WR#/SPI_O SLMM#/SPI_S# PIO/SLIO# PIO/_S# K L PIO/NUML PIO/_TMR/PL PIO/_INT/SRL SPI_SL# IMM_ TV_# JN R L_WLN# NH_P RUN_ JN K_I _I _R# _S# _L T R.UY PTUR# L_NUM# L_P# L_SR# VLW TP TP _NR _R TP TP _NR TP TP TP.UY L Lm_.UY P _OPPR _ MR_ T_PWR_# WLN_PWR L_HR# L_T# L_LUTOOTH# L_WLN# NH_P NH, PR_H SUS_ RSMRST#, LNRST# PIO _FSO _FSO R _L TLK_M, TT_M, SM_PU_LK SM_PU_T PTUR# FN_TH R--J FN_ PM_ L_NUM# L_P# L_SR# VLW LN_WOL_N, PM_S_STT# R _WR# _PN For MI / UY / MS- VR_ R=N VR_ VLW R _KR R use % or %? R.KR% SPI_HOL# VLW _R# _WR# _S# _SPILK R R _IN _OUT TLK_M VLW TT_M _I High :MT Mode _I Low :Non MT Mode To MM & attery & S(SF micro p) To PU / For MI _SPILK/ HHS-.PITH_WHIT-RH ROM Interface Now VR_ is controlled by HW heck with which pins need to be reversed for debug PN I _PN lose to U YT.KHZ.P_S-RH- _IN LOS TO HIP _OUT is reserved for new version (nm process) / change to new part _UY For leakage current issue Vr=.V,Ir will be more than u.uy S-SWS_SO-RH R KR R MR% PN R R ROM _S# _R# / Update.KR.KR I _PN SPI_SL# KOUT VSUS VLW U # V SO HOL# WP# SK VSS SI MLM SPI_SL#:FLSH MO KOUT: ISP MO KOUT KOUT KIN KIN KIN KIN KIN KIN KIN KIN KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT KOUT Keyboard N. H/W Strap for N VLW.UY SPI_HOL# _SPILK _WR# High:IS Mode (PIO def. pull up) Low:SPI Mode (needed KR pull Low) High:Normal Mode (PIO def. pull up) Low:ISP Mode (needed KR pull Low) R R x-wh FP_S_ N-F-M KR _KR N.UY KSI# KSI# S-RV-_SO K_SI# R R R / R change to K R KR U KR H_T KSMI# H_T KSMI# S-RV-_SO _T S-RV-_SO K_SMI# VSUS U S-RV-_SO LLSYSP VSUS U LLSYSP JN _NR lose to U, MPWROK I _PN _VRUN_PWR U _SP_S R _R LNRST# _.U SP_S JN.U _NR _VIMM_P _VM_P PM_PWRTN# PM_PWRTN# S-RV-_SO K_PWRT# VR_ NWZ_S R KR% U NWZ_S JN _NR VF_PWR elete VTT_PWR VSUS VSUS / Reserved by Intel MT oc MSI ORPORTI K//uP (N) Size ocument Number Rev MS- Tuesday, February, ate: Sheet of

21 Q W M for hannel (by ) / FINRPRINT & TOUH P VRUN R R P-PM_SOT V_MR VRUN VRUN S STTP STTN STRN STRP ST H S N S S - S N S - S S N N N H NN-F- ST P Signal Segment Power Segment V V V N N N V V V N Reserved N V V V P P P P P P P P P P P P P P P VRUN.U / dd R, For MI (close to Q) MR_.U lose to. U.Y R R _PN VRUN R KR R MR R KR /MR_# S VRUN R KR.U USPP M_# USPN Q N SOTS_T L _M-L--T R _KR VRUN R.KR PTUR / hicony (N) or M (hannel) OM OPT PN U.- PN R VRUN.U M module is V or V? R PTUR MIRROR# MIRROR# R HHS-.PITH_WHIT-RH / dd R For MI (close to ) USPN USPP UY.U UY.U L M-L--T TP_T TP_LK I _PN _PN / S-VL NT-RH I S-VL NT-RH N N-F-M FP_S_ PTUR# To K control pin PIO (for channal) PTUR# S Q _N-RHUN R _R.KR MIRROR# R _R USPN TP_T USPP TP_LK Rlamp Rlamp SOT SOT --S --S For MI S solution USV_ USPP USPN VRUN USPP USPN / Modify to.uf For MI VRUN F USV_ US NTOR USPN USPN# P UY P STUS N-M- N-M-T ST_RP_ LI _M-L--T S-IP F-SMPTF--RH.U USPP# USPP u. P USPP USPP# L M-L--T _PN _PN VUS - N SMT ST_US ST_US-RH N T T- N R- R N ST_RP_ ST_RN_ ST_TN_ ST_TP_ LOS ST N.U.U.U.U ST_RP ST_RN ST_TN ST_TP ST_RP ST_RN ST_TN ST_TP ST_RN_ ST_TN_ LI _M-L--T USPN USPN# L M-L--T _PN US _PN USM_LK-RH- N-M- ST_TP_ ST ROM/V VRUN VRUN 板下 TO US OR NTOR VRUN N STTP STTN STRN STRP L_H# U SP_S.U S N P P S T V P S T# V P S N M P S R# N P S R N P S N ST R R KR ST_TIV# VRUN KR VRUN U.Y.U USPN USPP L _M-L--T _PN _PN T_PWR_# LUTOOTH.U N VRUN R _R HNNL_LK R _R HNNL_T VRUN R _KR P R _HS_white-.pitch N--H _KR _ / Update / dd by MI / N / No Stuff by Neo USPN USPP USPN USPP / Swap for layout M NT: ottom US NT: ottom able: 金屬 pin 同面 Pin define: Reverse _PN / For MI _PN _u. _PN _PN H,ROM,ST,LUTOOTH,US N. Size ocument Number Rev MS- N-F-M FP_S_ MSI ORPORTI Tuesday, February, ate: Sheet of

22 M_V# R KR VRUN Q P-PM_SOT S MR_V _.U.Y _VRUN L L. _VRUN_R VRUN.u..U.U.u. L L. VRUN lose to conn MR_V.u. VRUN _VRUN_R MR_V _V S_V MS_V.U.U _R/ _R# _R/# S_M _# _R# S L _# S L _L S W# _L S WPO _W# S_LK MS_/ WP# S_WP_SW MS_/ S SW MS_/ MS_S/ SW MS_/ _ S/MS_LKOUT in-n MS_# MS_SLK MS_S/_ R R MS_S MS_INS in-n MS_/_ R R MS_ MS_S MS_/_ R R MS_ MS_ N MS_/_ R R MS_ MS_ MS_/_ R R MS_ MS_ N MS_ IN_ard Reader conn_p _R/ I _PN- _R# I _PN- _# I _PN- _L I _PN- _L I _PN- _W# I _PN- _WPO I _PN- MS_/_ I _PN- MS_/_ I _PN- MS_/_ I _PN- MS_S/_ I _PN- _ I _PN- _ I _PN- _ I _PN- MS_/_ I _PN- S_M I PN S_ I PN S_ I PN S_ I PN S_ I PN / Modify by MI S/MS_LK R R S/MS_LKOUT S_MIN R S_IN R S_IN R S_IN R S_IN R S/MS_LKOUT SM_WPI#/S_WP S_# _# R R R R R.U / Modify by MI S_M S_ S_ S_ S_ PI_ PI_[:] PI_# PI_# PI_# PI_# R PI_VSL# PI_FRM# PI_IRY# PI_TRY# PI_STOP# PI_PR PI_RQ# PI_NT# R_RST# INT_PIRQ# PI_PM# R PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_# PI_# PI_# PI_# ISL PLK_RIN PI_VSL# PI_FRM# PI_IRY# PI_TRY# PI_STOP# PI_PR PI_RQ# PI_NT# R LK_RUN# TP.u..U _R U /# /# /# /# ISL PI_LK VSL# FRM# IRY# TRY# STOP# PR RQ# NT# PI_RST# INT# PM# LKRUN# MI_TV OZ PI_V PI_V.V.V.V.V.V.V.V.V OZ N N N N N N N N N N N.V.V.V.V.V.V.U RF I O IS TP TP- TP TP- N N N N N N N N M_V# S/MS_LK S_ S_ S_ S_ S_SM SM_WPI#/S_WP S_# N N N N N N MS_/ MS_S/_ MS_/_ MS_/_ MS_/ # _R/# _L _L _W# _R# _WPO# MS_# _# TST TST L.U OZ_RF _I _O TPIS TPP TPN TPP TPN R M_V# S/MS_LKIN S_ S_ S_ S_ S_M SM_WPI#/S_WP S_# MS_/ MS_S/_ MS_/_ MS_/_ MS_/ # _R/ _L _L _W# _R# _WPO MS_# _#.U Media I/F _R/ _R# _# _L.K% pn pn Y.MHZ_SM. _I _O lose to chip S ard Memory Stick x ard _R/ _R# _# _L I PN Lm- _L _W# _L _W# _WPO _WP# lose to, P_LKRUN# R R _R _KR LK_RUN# MS_/_ MS_/_ MS_/_ MS_ MS_ MS MS_S/_ MS_S _ TPIS close to chip R.R% TPN TPP TPP TPN R R.R%.R%.R% UY R R close to chip P.K% L M-L--M L M-L--M TP# TP TP# TP N N MP_-_I TPP and TPN swap S/MS_LKIN PLK_R R R lose to U / Modify by MI R R S/MS_LK _PN PLK_RIN _PN MS_/ # S/MS_LK MS_# S_M S_ S_ S_ S_ SM_WPI#/S_WP S_# MIRO-STR INT'L O.,LT. O_ard reader Size ocument Number Rev MS- MS SW S_LK MS_LK MS_INS S_M S_ S_ S_ S_ S_WP_SW S SW Tuesday, February, ate: Sheet of

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