1215N Rev: 1.00

Transcription

1 SHEMTI Revision. E PGE ontent SYSTEM PGE REF. PU()_MI,PEG,FI,LK,MIS PU()_R PU()_FG,RSV, IM-R SO-IMM HNNEL IM-R SO-IMM HNNEL IM-R VREF & TERMINTION 0 PH_IEX()ST,IH,RT,LP PH_IEX()_PIE,LK,SM,PEG PH_IEX()_FI,MI,SYS PWR PH_IEX()_POWER, PH_SPI ROM,OTH LK_ ISLPRSGLFT 0 E_ K0QF K R REER U UG-EUG PORT HMI ONN RT-LVS ONN RT--SU ONN 0 FN-THERML SENSOR, FN ONN X-ST H ONN US-US.0 ONN* MINI-PIE WLN ONN LE- PWR,LE,FP ONN SG-ISHRGE IRUIT 0 _-, TT ONN T_-LUETOOTH ONN LI ME_-SREW HOLE, SMT NUT RT_ ON MO-MOS MER oard to oard ONN OTH-EXPRESS GTE 0 VG_nVII_NM-GE_PIE VG_nVII_NM-GE_F VG_nVII_NM-GE_isplay VG_nVII_NM-GE_XTL VG_nVII_NM-GE_GPIO G_nVII_NM_0nm_R G-Power History Power On Sequence PGE ontent POWER PGE REF. 0_W_VORE(RT) _PW_SYSTEM(RT0) _PW_IO_VP(RT0) _PW_IO_R(RT0+uP) _PW_GPU_NV_ORE(RT0) _PW_+.VS _POWER_HRGER _POWER_LO SWITH _POWER_FLOWHRT _POWER_Latch SUSTeK OMPUTER IN PGE REF. riesjesse ustom ate: Monday, May, 00 Sheet of E.0

2 SYSTEM PGE REF. PGE ontent PU()_MI,PEG,FI,LK,MIS PU()_R PU()_FG,RSV, IM-R SO-IMM HNNEL IM-R SO-IMM HNNEL IM-R VREF & TERMINTION 0 PH_IEX()ST,IH,RT,LP PH_IEX()_PIE,LK,SM,PEG PH_IEX()_FI,MI,SYS PWR PH_IEX()_POWER, PH_SPI ROM,OTH LK_ ISLPRSGLFT 0 E_ K0QF K R REER U UG-EUG PORT HMI ONN RT-LVS ONN RT--SU ONN 0 FN-THERML SENSOR, FN ONN X-ST H ONN US-US.0 ONN* MINI-PIE WLN ONN LE- PWR,LE,FP ONN SG-ISHRGE IRUIT 0 _-, TT ONN T_-LUETOOTH ONN LI ME_-SREW HOLE, SMT NUT RT_ ON MO-MOS MER oard to oard ONN OTH-EXPRESS GTE 0 VG_nVII_NM-GE_PIE VG_nVII_NM-GE_F VG_nVII_NM-GE_isplay VG_nVII_NM-GE_XTL VG_nVII_NM-GE_GPIO G_nVII_NM_0nm_R G-Power History Power On Sequence 0_W_VORE(RT) _PW_SYSTEM(RT0) _PW_IO_VP(RT0) _PW_IO_R(RT0+uP) _PW_GPU_NV_ORE(RT0) _PW_+.VS _POWER_HRGER _POWER_LO SWITH _POWER_FLOWHRT _POWER_Latch IO oard IO oard N SHEMTI Revision.00 LOK IGRM HMI RT Page Page L Panel Page Touchpad Page Keyboard INT. MI udio mp Jack Page US.0 US.0 RJ IO oard IO oard IO oard IO oard HMI Nvidia NM ebug onn. E K0QF SPI ROM Page 0 zalia odec Realtek L Page 0 LVS RT MOS amera IO oard NE US.0 R IO oard LN R IO oard Page Page 0 IO oard PIE x US PIE x PIE x zalia LP IO oard lock Generator ISLPRSGLFT PU PineTrail 0 Page NM0 MI x ST 0 Page ~ Page 0~ R 00 PIE x US H() Page ischarge ircuit Page 0 Miniard WiFiWiMax US Port() US Port() US Port() & TT. onn. R SO-IMM ardreader U Page 0 Page ~ IO oard IO oard IO oard Page ardreader Power VORE System PW_IO_VP PW_IO_R MOS amera Miniard WiFiWiMax luetooth Page 0 Page Page Page PW_GPU_NV_ORE IO oard harger PW_+.VS Load Switch POWER_Latch. Page Page Page Page Page Page Page Page PWM Fan Page 0 Reset ircuit Page Skew Holes Page SUSTeK OMPUTER IN. N lock iagram riesjesse Monday, May, 00 ate: Sheet of.0

3 +VS.KOhm RN00.KOhm RN00.KOhm RN00.KOhm RN00 R.K H_PMN_0 H_PMN_ H_PMN_ H_PMN_ REF KT PU EI_T_PH EI_LK_PH L_TL_T L_TL_LK LVS_LLKN_PH LVS_LLKP_PH LVS_L0N_PH LVS_L0P_PH LVS_LN_PH LVS_LP_PH LVS_LN_PH LVS_LP_PH.KOhm R00 R00 R00 L_KEN_PH L_KLTTL_PH EI_LK_PH EI_T_PH L_VEN_PH 00KOhm R0 00KOhm R0 H_PMN_0 H_PMN_ H_PMN_ H_PMN_ T00 L_VEN_PH L_KEN_PH H_LIG R J H_LVREFH N H_LVREFL N L L L_TL_LK L L_TL_TK K K H H_PMN_0 H_PMN_ H_PMN_ H_PMN_ I to control L backlight, Type IO. U U R R N N R R G E G F U00 L_LKN L_LKP L_TN_0 L_TP_0 L_TN_ L_TP_ L_TN_ L_TP_ PRSTP# PSLP# LIG INIT# LVG PRY# LVREFH PREQ# LVREFL LKLT_EN THERMTRIP# LKLT_TL LTL_LK LTL_T PROHOT# L_LK PUPWRGOO L_T LV_EN PM 0# PM # PM # PM # SMI# 0M# FERR# LINT0 LINT IGNNE# STPLK# GTLREF VSS RSV RSV0 LKN LKP E H H F0 F E F G G0 G E F E W H PROHOT# L T00 E T00 H0 J0 Reserved for debug H_SMI# 0 H_0M# 0 H_FERR# 0 H_INITR 0 H_NMI 0 H_IGNNE# 0 PU_STPLK 0 PM_PRSTP# PM_PSLP# H_INIT# 0 H_PMN_RY# H_PMN_REQ# H_THEMTRIP# 0 LK_PU_LK# LK_PU_LK RN0 XP H_PMN_0 PU_SEL0 RN0 XP H_PMN_ PM 0#RSV SEL_0 K T0 0OHM PU_SEL 0OHM 0 RN0 XP H_PMN_ PM #RSV SEL_ H T0 PU_SEL 0OHM 0 H_PMN_ PM #RSV SEL_ K T0 RN0 XP 0OHM PM #RSV VR_VI0 +VP VI_0 H0 VR_VI VI_ H VR_VI NU_PG VI_ H R00 Ohm G VR_VI RSV VI_ G0 VR_VI H_TI TI VI_ G VR_VI H_TO TO VI_ F VR_VI H_TK TK VI_ E H_TMS TMS NU_PL H_TRST# TRST# RSV L T0 NU_P0 RSV 0 T0 NU_P PU_THRM_ RSV H T0 NU_P 0 PU_THRM_ 0 PU_THRM_ THRM_ RSV T0 0 PU_THRM_ E0 THRM_ RSV_TP K T00 RSV_TP T00 0 PU_EXTGREF THRM_RSV EXTGREF K T00 T0 THRM_RSV Reference voltage.near PVN side. 00 UF.V PU_GTLREF 00 0PF0V VR_VI[:0] 0 00 UF.V R0 KOhm H_THEMTRIP# +VP R00 00 KOhm UF.V % R0 +VP % OHM R00.KOhm % 00 UF.V +VP R0 Ohm R00 H_PMN_0 H_PMN_ H_PMN_ H_PMN_ RN00 Ohm H_PMN_REQ# RN00 Ohm H_TI RN00 Ohm H_TMS RN00 Ohm H_PMN_RY# RN00 Ohm RN00 Ohm RN00 Ohm RN00 Ohm H_TO RN00 Ohm RN00 Ohm H_TK RN00 Ohm H_TRST# RN00 Ohm +VP H_PROHOT_S# 0 H_PWRG, The rising time of PUPWRGOO should be small than 0ns and rising edge should be monotonicity +VP R0 KOhm % Place Near PU XP XP XP XP XP XP XP XP Ohm XP R0 +VP U00 MI_TXP0 MI_TXN0 MI_TXP MI_TXN F F H G MI_RXP_0 MI_RXN_0 MI_RXP_ MI_RXN_ MI_TXP_0 MI_TXN_0 MI_TXP_ MI_TXN_ G G H J MI_RXP0 MI_RXN0 MI_RXP MI_RXN _PIE_N# _PIE_N T00 T0 T00 T00 MI_TXP MI_TXN MI_TXP MI_TXN N N R0 R N0 N K J M L EXP_LKINN EXP_ROMPO EXP_LKINP EXP_IOMPI EXP_RIS EXP_TLKINN EXP_TLKINP RSV_TP SV RSV_TP RSV RSV RSV RSV RSV0 RSV RSV RSV RSV L0 L L N P K L M N GIROMP EXP_RIS T00 T00 MI_RXP MI_RXN MI_RXP MI_RXN R00 0OHM % R00.Ohm % SUSTek omputer IN. PineView_ riesjesse ate: Monday, May, 00 Sheet of.0

4 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q RVREF M Q M Q RRP M Q M Q RRPU M QS M QS M QS0 M QS# M QS# M QS M M M M M QS M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M QS M M M QS# M M M Q M M M Q M QS# M Q M M0 M Q M Q M Q M Q M Q0 M 0 M Q M Q M M QS M Q M QS# M Q M M M M Q M M Q0 M Q M M Q M Q M M Q M Q M M Q M Q M M M QS# M Q M Q M M QS# M Q M Q0 M M M M Q M Q M M QS#0 M Q M Q M M QS M Q M M Q M 0 M Q M Q M_RMRST# R_PWROK M_RMRST#_J R_PWROK +.V +.V +V +.V +.V M QS#[:0], M QS[:0], M Q[:0], M M[:0], M WE#, M S#, M RS#, M S0, M S, M_S#0 M S, M_S# M_OT M_OT0 M_KE M_KE0 M_LK_R0 M_LK_R#0 M_LK_R# M_LK_R M [:0], M_S# M_S# M_KE M_KE M_OT M_OT M_LK_R M_LK_R M_LK_R# M_LK_R# R_PWRG SUS_ON 0,, M_RMRST#, ate: Sheet of ustom Monday, May, 00 SUSTek omputer IN. PineView_.0 riesjesse ate: Sheet of ustom Monday, May, 00 SUSTek omputer IN. PineView_.0 riesjesse ate: Sheet of ustom Monday, May, 00 SUSTek omputer IN. PineView_.0 riesjesse Near MH Pin L SL00 close to PU PR R00 KOhm % R00 KOhm % T00 T00 R M_0 H R M_ J R M_ K R M_ K R M_ J R M_ H R M_ K R M_ J R M_ H R M_ K R M_0 K0 R M_ H R M_ J R M_ J R M_ J0 R WE# K R S# J R RS# K R S_0 J0 R S_ H0 R S_ K R S#_0 H R S#_ K R S#_ J R S#_ J R KE_0 H0 R KE_ H R KE_ K0 R KE_ J R OT_0 K R OT_ H R OT_ H R OT_ K R K_0 G R K_0# F R K_ R K_# R K_ R K_# R K_ F R K_# G RSV RSV RSV RSV RSV RSV K RSV_TP RSV_TP R_VREF L R_RP K R_RPU J RSV K R QS_0 R QS#_0 R M_0 R Q_0 R Q_ R Q_ F R Q_ G R Q_ R Q_ R Q_ E R Q_ E R QS_ R QS#_ R M_ R Q_ R Q_ R Q_0 E R Q_ G R Q_ R Q_ R Q_ R Q_ R QS_ R QS#_ 0 R M_ E R Q_ G R Q_ G R Q_ F0 R Q_ G R Q_0 F R Q_ F R Q_ R Q_ E0 R QS_ K R QS#_ K R M_ J R Q_ H R Q_ J R Q_ K R Q_ J R Q_ F R Q_ H R Q_0 L R Q_ J R QS_ G R QS#_ G R M_ R Q_ E R Q_ G R Q_ F R Q_ R Q_ G R Q_ F R Q_ E R Q_ R QS_ E R QS#_ G R M_ J R Q_0 E R Q_ G R Q_ R Q_ R Q_ R Q_ G R Q_ R Q_ E R QS_ E0 R QS#_ F R M_ F0 R Q_ G R Q_ G0 R Q_0 0 R Q_ R Q_ J0 R Q_ J R Q_ E R Q_ R QS_ R QS#_ R M_ R Q_ R Q_ R Q_ W R Q_ W R Q_0 R Q_ R Q_ R Q_ W U00 U00 R00 R00 T00 T00 T00 T00 T00 T UF0V 00 0.UF0V Q00 UMKN Q00 UMKN R00 00KOHM R00 00KOHM R00 R UF0V 00 0.UF0V Q00 UMKN Q00 UMKN 00 SL00 00 SL00 T00 T00 00 UF.V 00 UF.V T00 T00 R00 R00 T00 T00 R00 0KOhm N R00 0KOhm N R00 0.Ohm R00 0.Ohm R00 0KOhm R00 0KOhm R00 KOhm % R00 KOhm % R00 0.Ohm R00 0.Ohm

5 LK&T need.k Pull up to +VS(Or may we can use.k);connector side has pull-up resistor. U00 RT_HSYN_R R00 Ohm XP_RSV[0] RT_HSYN M0 RT_HSYN_PH RT_VSYN_R R00 Ohm XP_RSV[] RT_VSYN M RT_VSYN_PH +VS XP_RSV[] XP_RSV[] RT_RE N RT_RE_PH RT_GREEN_PH R0 KOhm XP_RSV XP_RSV[] RT_GREEN P0 XP_RSV[] RT_LUE P RT_LUE_PH RT_RE_PH XP_RSV[] RT_IRTN N0 R00 % RT_GREEN_PH R00 % XP_RSV[] RT_LUE_PH R00 % R00 KOhm XP_RSV XP_RSV[] XP_RSV[] RT T L _T_PH _LK_PH R0 KOhm XP_RSV XP_RSV[0] RT LK L0 XP_RSV[] 0 REFSET R00 % Ohm XP_RSV[] _IREF P 0 _T_PH RN00 XP_RSV[].KOhm _LK_PH _M_N RN00 XP_RSV[] REFLKINP Y0.KOhm 0 XP_RSV[] REFLKINN Y _M_N# R0 KOhm XP_RSV _L_LVS XP_RSV[] REFSSLKINP 0 XP_RSV[] REFSSLKINN _L_LVS# R00 PM_PRSLPVR,0 L T00 RSV +VS PM_EXTTS 0KOhm R00 RSV K PM_EXTTS0# 0KOhm R00 RSV J0 PWROK L PM_PWROK,0 SPLTRST# RSV_TP RSTIN# SPLTRST#, T00 T00 RSV_TP R T00 RSV_TP0 R _FS_N# T00 RSV_TP HPL_LKINN W HPL_LKINP W _FS_N 0PF0V 0PF0V T00 RSV_TP W MHZ T00 RSV_TP T T00 RSV_TP V T00 RSV_TP Intel confirm only RSV need stuff K resistor. 0 MI x Strap P:MI X ; Umount:MI X SUSTek omputer IN. ate: Monday, May, 00 Sheet of ustom PineView_ riesjesse E E E E E E E F F F F F G0 G H H H H H H J J J K K K K0 K L L L L L L L0 L 0 E E0 E E E E F F VSS VSS VSS RSV_NTF RSV_NTF RSV_NTF RSV_NTF VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS RSV_NTF VSS RSV_NTF RSV_NTF RSV_NTF VSS RSV_NTF RSV_NTF0 VSS VSS0 RSV_NTF VSS RSV_NTF RSV_NTF RSV_NTF VSS VSS VSS VSS VSS RSV_NTF RSV_NTF VSS VSS RSV_NTF VSS VSS0 VSS VSS RSV_NTF VSS RSV_NTF VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS F F F G G G G G H H H H H H J J J J K K K K K K K0 K K L L L L L L L M M N N N N N N N N N P P P P P P P P R R R T U U U U V V V V V W W W W W W W0 W W W W Y Y Y T U00F

6 U00E +VORE T00 TPT 0 00UF.V +VP +.V UF.V 0UF.V +0.VS_GMH R00 r00_h 0 00UF.V + Intel recommander for R T T T T T V V UF.V UF.V UF.V W W W W +.V K L U0 0.0UFV 0.UF0V 0UF.V 0UF.V U U U U U V +VP V V W0 L00 W UF.V 0UF.V 0UF.V 0.UF0V UF.V 00Mhz l UF.V UF.V +.VS +.0_HMPLL V R00 r00_h +VSFR_PLL +.VS L00 00Mhz +VRT_R T0 l00 +VS VP 00 0 UF.V 0.UF0V T UF.V 0.UF0V J UF.V UF.V 0UF.V UF.V 0.UF0V 0 0UF.V 0 UF.V 0 0.0UFV 0 0 UF.V UF.V UF0V 0.UF0V 0 UF.V K K K L L L L VGFX VGFX VGFX VGFX VGFX VGFX VGFX VGFX VGFX VGFX0 VGFX VSM VSM VSM VSM VSM VSM VSM VK_R VK_R V_R V_R V_R V_R V_R V_R V_R V_R V_R V_R0 V_R VK_R VK_R V PL V_HMPLL VSFR PL VRT V_GIO VRING_EST VRING_WEST_ VRING_WEST_ VRING_WEST_ V_LGI V V V V V V V V V V0 V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V VSENSE VSSSENSE V V VP VP VLVS VLVS V_MI V_MI V_MI VPLL_MI VSFR_MIHMPLL VP E E E F F F G G G H H H H J J J J K K K L L L L N N N N Y V0 W T T T P E 0 UF.V +VP +V_LV +V_MI 0 UF.V +V 0 0.UF0V T00 TPT +VSFR_MIPLL +VP UF0V 0.UF0V 0.UF0V +.VS L0 00Mhz VORE_V_SENSE 0 VORE_VSS_SENSE 0 +.VS UF.V 0UF.V 0 UF.V 00 0.UF0V UF.V 00 0.UF0V UF0V 0.UF0V 0.UF0V 0.UF0V L00 00Mhz 0 UF.V c00 +.VS +VP R00 r00_h 0 0.UF0V 00 UF.V 0 0.UF0V 0 UF.V 00 UF.V 0 0UF.V +.VS V =. V =0.0 VGFX =. VLVS, VLVS=0.0 V_MI =0. urrent for PineView VSFR_MIHMPLL =0.0 V_R and VK_R =. VSM and VK_R =. VRING_EST, VRING_EST_WEST, V_LGI, V PL, V_HMPLL =0. V_GIO =0.00 VSFR PL, VRT =0. 0 UF.V L00 00Mhz l00 SUSTek omputer IN. PineView_ riesjesse ustom ate: Monday, May, 00 Sheet of.0

7 M Q M QS M M M Q M Q M QS#[:0] M_LK_R0 M QS M Q M Q M QS[:0] M M_LK_R#0 M Q M Q M M M Q M QS# M M QS M Q M Q0 M Q M Q0 M S0 M QS# M QS# M M M Q M M M QS M 0 M M0 M QS#0 M Q M QS# M Q M M M Q M QS M QS M S M QS# M 0 M Q M Q M Q M Q M Q M Q M_LK_R# M M M_LK_R M M Q M M M QS0 M M QS# M Q M M Q M Q[:0] M QS# M Q M Q M Q M M M M Q M M QS M Q M M M Q PM_EXTTS0#_J0 M M M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M_VREFQ_IMM0 +.V +0.VS +.V +VS M_VREF_IMM0 +.V +0.VS M_LK_R0 M WE#, M RS#, M M[:0], M S#, M_LK_R M_LK_R#0 M S, M_OT M_S# M S, M_OT0 M QS#[:0], M_S#0 M Q[:0], M QS[:0], M S0, M_KE M [:0], M_KE0 M_RMRST#, M_LK_R# PM_EXTTS0# SM_T_S,, SM_LK_S,, ate: Sheet of ustom Monday, May, 00 SUSTek omputer IN. R SO-IMM_0.G riesjesse ate: Sheet of ustom Monday, May, 00 SUSTek omputer IN. R SO-IMM_0.G riesjesse ate: Sheet of ustom Monday, May, 00 SUSTek omputer IN. R SO-IMM_0.G riesjesse SWP R. SWP SWP SWP SWP Place near SO-IMM_0 SWP SWP.:0 SWP 0 0PF0V 0 0PF0V 00 UF.V 00 UF.V 0 0.UF0V 0 0.UF0V 00 0.UF0V 00 0.UF0V 00 SL00 00 SL UF.V 00 0UF.V R00 R00 0 0PF0V 0 0PF0V 00 0.UF0V 00 0.UF0V EVENT# 0 0 N N NP_N 0 NP_N 0 TEST V V0 00 V 0 V 0 V V V V V V V V V V V V V V VSP VREF VREFQ VSS VSS 0 VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VTT 0 VTT 0 J00 R_IMM_0P J00 R_IMM_0P 00 0UF.V 00 0UF.V 0 0.UF0V 0 0.UF0V 00 0UF.V 00 0UF.V UFV UFV 00 0UF.V 00 0UF.V 0.UF.V 0.UF.V 0 0UF.V 0 0UF.V 0 UF.V 0 UF.V 0 0.UF0V 0 0.UF0V 00.UF.V 00.UF.V 00 SL00 00 SL00 0.UF.V 0.UF.V 00 0.UF0V 00 0.UF0V 00 0.UF0V 00 0.UF0V 0 0P 0 # S# K0# 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q QS#0 0 QS# QS# QS# QS# QS# QS# QS# QS0 QS QS QS QS QS QS QS S# S0# OT 0 OT0 WE# RS# 0 S 0 S0 SL 0 S 00 RESET# 0 J00 R_IMM_0P G00 R IMM 0P,.V.H,ST J00 R_IMM_0P G00 R IMM 0P,.V.H,ST

8 M Q M Q0 M Q M Q M Q M QS M Q M M M_a_QS M Q M QS# M S0 M Q M M M M QS# M M Q M Q M_LK_R M M M QS# M M M Q M M M M M Q M Q PM_EXTTS0#_J0 M_LK_R M Q M QS[:0] M QS#[:0] M M Q M_LK_R# M Q M Q M 0 M Q M Q M QS0 M Q M M QS M QS M_LK_R# M M QS M Q M M M QS# M QS M M QS# M M QS# M QS#0 M S M M M M QS# M Q M Q M M M0 M M M Q[:0] M QS M Q0 M 0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q +.V +.V +0.VS +VS +0.VS M_VREFQ_IMM M_VREF_IMM +.V +VS +.V M_OT M WE#, M_S# M_LK_R M_LK_R# M_LK_R# M [:0], M QS[:0], M_RMRST#, M Q[:0], M RS#, PM_EXTTS0# M_KE M M[:0], M S, M_LK_R M S#, M_KE M S0, M QS#[:0], M S, M_OT M_S# SM_LK_S,, SM_T_S,, ate: Sheet of ustom Monday, May, 00 SUSTeK OMPUTER IN. N R SO-IMM_.00 riesjesse ate: Sheet of ustom Monday, May, 00 SUSTeK OMPUTER IN. N R SO-IMM_.00 riesjesse ate: Sheet of ustom Monday, May, 00 SUSTeK OMPUTER IN. N R SO-IMM_.00 riesjesse SWP SWP.:H SWP SWP SWP Place near SO-IMM_ SWP SWP SWP R UFV UFV 00 0.UF0V 00 0.UF0V 00 0.UF0V 00 0.UF0V 00 SL00 00 SL00 0 0P 0 # S# K0# 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q QS#0 0 QS# QS# QS# QS# QS# QS# QS# QS0 QS QS QS QS QS QS QS S# S0# OT 0 OT0 WE# RS# 0 S 0 S0 SL 0 S 00 RESET# 0 J00 R_IMM_0P G00 J00 R_IMM_0P G UF0V 0 0.UF0V 00 0.UF0V 00 0.UF0V UFV UFV UFV UFV 00.UF.V 00.UF.V 0.UF.V 0.UF.V 0 0PF0V c00 0 0PF0V c UF0V 0 0.UF0V 00 0.UF0V 00 0.UF0V 0 UF.V 0 UF.V 00 UF.V 00 UF.V 0 0.UF0V 0 0.UF0V 0 0UF.V 0 0UF.V 00 SL00 00 SL00 0 0PF0V c00 0 0PF0V c00 0.UF.V 0.UF.V 0 0.UF0V 0 0.UF0V 0 0UF.V 0 0UF.V EVENT# 0 0 N N NP_N 0 NP_N 0 TEST V V0 00 V 0 V 0 V V V V V V V V V V V V V V VSP VREF VREFQ VSS VSS 0 VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VTT 0 VTT 0 J00 R_IMM_0P J00 R_IMM_0P R00 R00 00 UF.V 00 UF.V 00 0UF.V 00 0UF.V 0 0.UF0V 0 0.UF0V 00 0UF.V 00 0UF.V

9 efault M M_VREF M: Fixed SO-IMM VREF_Q (efault Stuffing) *Option: Mount=R0,R0,R0,R0,R0 Unmount=M block, except R0 R M_VREF_IMM0 SL00 M_VREF_IMM SL00 SHORT_PIN shortpin_r00 For R_VREF command & address. SHORT_PIN shortpin_r00 R0,R0 are always mount. +.V M_VREF SL00 SL00 SHORT_PIN shortpin_r00 M_VREFQ_IMM0 M_VREFQ_IMM R00 0KOhm % SHORT_PIN shortpin_r00 R00 0KOhm % SUSTeK OMPUTER IN. N R Vref riesjesse ate: Monday, May, 00 Sheet of.00

10 Main oard SUSTeK OMPUTER IN. N N_**** *** ustom ate: Monday, May, 00 Sheet 0 of.00

11 Main oard SUSTeK OMPUTER IN. N N_**** *** ustom ate: Monday, May, 00 Sheet of.00

12 Main oard SUSTeK OMPUTER IN. N N_**** *** ustom ate: Monday, May, 00 Sheet of.00

13 0, LK_PIE_US_PH_IO 0, LK_PIE_US#_PH_IO U_O U_O 0, 0, _UN UP_ PIE_RXP_US_IO PIE_RXN_US_IO R 0KOhm US.0 +V_U 0, 0, PIE_TXP IO PIE_TXN IO PIE_WKE_US# 0 0 R0 0KOhm US.0 PI Express Interface trace 最最最最最.cm( inches). _UTXP UTXN_ +V_U _UTXP UTXN UN UP URXP URXN_,0, 需需 S 端 pull high. _URXP URXN_ R US_NE R US_NE UF_PLT_RST#_IO +V_U.KOhm.KOhm.KOhm 0.UFV US_NE R US_NE R US_NE PR change to 0ohm US_NE 0.UFV US_NE 0.UFV R US_NE R0 US_NE 0 0 T0 LK_PIE_US_PH_IO_NE LK_PIE_US#_PH_IO_NE LKREQ_US# RN0 RN0 RN0 0.UFV US_NE X_UX_RXP_ X_UX_RXN_ PIE_TXP IO_NE PIE_TXN IO_NE US_NE U_PSEL US_NE U_UXET US_NE _UTXP NE _UTXN NE _UN NE _UP NE 0.UFVUS_NE _URXP NE 0.UFVUS_NE_URXN NE T0 TPb U_PPON U_PPON U_PPON 0.UFV US_NE R US_NE R US_NE PR change to 0ohm 0.UFV US_NE 0 0.UFV US_NE ()US.0 Interface trace 最最最最最 0cm( inches). ()US Interface differential trace torlerence = 0.mm( mail). T0 TPb 0.UFV US_NE U_PPON U_O U_O _UTXP NE _UTXN NE _UN NE _UP NE _URXP NE _URXN NE F F H K K J J 0 0 N0 P0 J H H G N P U0 PELKP PELKN PETXP PETXN PERXP PERXN PERST PEWKE PEREQ PSEL UXET UTXP UTXN UM UP URXP URXN PPON PPON OI OI UTXP UTXN UM UP URXP URXN PI Express Interface US Interface +.V Power Supply +.0V Power Supply V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V0_ V0_ V0_ V0_ V0_ V0_ V0_ V0_ V0_ V0_ V0_0 V0_ V0_ V0_ V0_ V0_ V0_0 V0_ V0_ V0_ F F 0 F G G L L0 L L N N N P E E E E H H L L H K K +V_U 0 0.UFV US_NE 0.0UF0V US_NE 0 0.0UF0V US_NE 0 0.0UF0V US_NE 0 0.0UF0V US_NE 0.0UF0V US_NE +.VS_P_V 0 0.UFV US_NE 0.0UF0V US_NE 0 0.UFV US_NE 0.0UF0V US_NE 0 0.0UF0V US_NE 0 0.0UF0V US_NE 0.0UF0V US_NE 0 0.UFV US_NE 0.0UF0V US_NE 0. eta Standard ircuit _IO US.0 up000 _IO REV. U_0 ET _IO UP000 XUP000 _IO _IO _IO _IO _IO _IO _IO _IO +V_U +V_U UMKN 0KOhm R PIE_WKE#_IO,0, Q0 PIE_WKE_US# +VS_IO +VSUS_IO +V_U R0 US_SUS JP0 R SL0 JP0 00 (00m) US_VS MM_OPEN_MIL +.VS_P_V +.VS_P MM_OPEN_MIL (00m) 0 SPI_I_IO 0 SPI_S IO 0 SPI_LK_IO 0 SPI_O_IO R US_NE R US_NE R US_NE R US_NE 從從從從從從可可從 SMI 的 GPI pin, PWR Plate is Main PWR. 0 PORST# SPI_I_IO_NE SPI_S IO_NE SPI_LK_IO_NE SPI_O_IO_NE U_SMI# M N M N H P SPISO SPIS SPISK SPISI SMI PONRST SPI Interface System Interface Signal nalog Power UV UV P US_NE 0 0.UFV _IO US_NE 0.0UF0V US_NE 0.0UF0V US_NE 0.UFV +U_V_UX_L US_NE PF0V _IO lose to P 00Mhz L0 US_NE 可可可可可可可可 MHz lock. 若若若若若若的 lock, 請請請 US.0 datasheet. 0 0 XI XO 0, R US_NE R US_NEX SMI IO +V_U R0 R0 _IO _IO XI_NE XO_NE U_SEL 0: Mhz ; : Mhz N00 Q0 US_NE R0 R.0,item urrent IOS does not implement US_SMI# for legacy function. S G N M P XT XT SEL U_SMI# UP000F-K- System lock US_NE nalog Signal UPVSS N _IO UVSS RREF UVSS P N U_RREF R0 %.KOhm US_NE P 與 N 的 Layout, 請請請請請 NE Layout guide_page. _IO _IO U0 VSS VSS00 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS0 VSS VSS E VSS VSS E VSS VSS E VSS VSS E VSS VSS F VSS VSS F VSS VSS F VSS VSS F VSS0 VSS F VSS VSS0 F VSS VSS F VSS VSS G VSS VSS G VSS VSS G VSS VSS G VSS VSS G VSS VSS G VSS VSS G VSS0 VSS UP000F-K- US_NE P P P P P P P N N N N M M M M0 M M M M M M M L L L L L L L L K K K K J J J J J J J J J H H H H H G G _IO US.0_NE SUSTEK OMPUTER IN nndy_wang 00P_IO Monday, May, 00 ate: Sheet of.

14 SUSTeK OMPUTER IN. N *** ate: Monday, May, 00 Sheet of.00

15 SUSTeK OMPUTER IN. N *** ate: Monday, May, 00 Sheet of.00

16 SUSTek omputer IN. R-SO-IMM *** Monday, May, 00 ate: Sheet of.g

17 SUSTeK OMPUTER IN. N R SO-IMM_ *** Monday, May, 00 ate: Sheet of.00

18 SUSTeK OMPUTER IN. N R Vref *** Monday, May, 00 ate: Sheet of.00

19 SUSTeK OMPUTER IN. N VI ontroller ustom ate: Monday, May, 00 Sheet of.00

20 U00 R E0 Y 0 Y0 W0 V E E U Y RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP ST_LKN ST_LKP STRIS# STRIS STLE# E E ST_TXN0_IH ST_TXP0_IH SMI# _ST_S# _ST_S STRIS# ST_LE#, 0.0UFV 0.0UFV SL00 00 H_FERR# R00.Ohm ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 H_SMI# R00 +VP Ohm +VP P_I0 P_I0 E E V 0 RSV RSV RSV RSV RSV RSV0 RSV RSV GPIO 0GTE 0M# PUSLP# IGNNE# INIT_V# INIT# INTR FERR# NMI RIN# SERIRQ SMI# STPLK# THERMTRIP# U THEMTRIP# 0GTE,0 Y0 H_0M# Y PU_PUSLP# T00 Y H_IGNNE# T00 H_INIT# H_INITR Y H_FERR# T H_NMI O_KRST#,0 F_SERIRQ,0 SMI# V PU_STPLK_R PU_STPLK 0 THEMTRIP# R00 R00 Ohm R00 H_THEMTRIP# SUSTeK OMPUTER IN. N PH_IEX()ST,IH,RT,LP riesjesse ate: Monday, May, 00 Sheet 0 of.00

21 +VS 0 For strapping as Top-block Swap override. _PI_S S_PIRST# T0 R0 KOhm R0 KOhm T0 PI_EVSEL# PI_IRY# PI_PME# PI_SERR# PI_STOP# PI_LOK# PI_TRY# PI_PERR# PI_FRME# PI_GNT# PI_REQ# PI_REQ# OOTSEL OOTSEL GPI GPIO PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# H0 PI_PIRQE# E PI_PIRQF# PI_PIRQG# H PI_PIRQH# F TOPLOK_SWP RSV K RSV M +VSUS J F 0 0 E G 0 G U00 PR EVSEL# PILK PIRST# IRY# PME# SERR# STOP# PLOK# TRY# PERR# FRME# GNT# GNT# REQ# REQ# GPIOSTRP# STRP#GPIO GPIO GPIO PIRQ# PIRQ# PIRQ# PIRQ# PIRQE#GPIO PIRQF#GPIO PIRQG#GPIO PIRQH#GPIO STRP0# RSV RSV E0# E# E# E# E H L J E0 E L G H H M L In P- emo KT has no PU RSV RSV PI_SERR# PI_PERR# PI_TRY# PI_STOP# PI_PIRQG# RN0 PI_PIRQ# RN0 PI_FRME# RN0 PI_EVSEL# RN0 PI_PIRQ# PI_PIRQF# PI_PIRQ# PI_PIRQ# PI_PIRQE# PI_LOK# PI_PIRQH# PI_IRY# GPIO GPI PI_REQ# PI_REQ# OOTSEL OOTSEL.KOhm R0.KOhm R0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 R0 R0 R0 STRP#GPIO STRP#GPIO Routing 0 : Flash ycles Routed to SPI 0: Flash ycles Routed to PI : Flash ycles Routed to LP.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM +VS 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 R0 KOhm KOhm KOhm KOhm +VS +VS 0 0.UFV 0 0.UFV R0 0KOhm PI_PME# Remain PILK. SUSTek omputer IN. PH_IEX()_PIE,LK,SM,PEG riesjesse ate: Monday, May, 00 Sheet of.0

22 +VP +RTT MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP +VMI_PLL_IH +V_T_R Near Tigerpoint. +V X_RT X_RT MI_RXN0_R MI_RXP0_R MI_TXN0_R MI_TXP0_R MI_RXN_R MI_RXP_R MI_TXN_R MI_TXP_R MI_RXN_R MI_RXP_R MI_TXN_R MI_TXP_R MI_RXN_R MI_RXP_R MI_TXN_R MI_TXP_R 0 PIEN_RXN0 0 PIEN_RXP0 0.UF0V PIEN_TXN0 0 PIEG_RXN0 0.UF0V PIEN_TXP0 0 PIEG_RXP0 PIE_RXN_MINIR PIE_RXP_MINIR 0 0.UF0V PIE_TXN PIE_TXN_MINIR 0 0.UF0V PIE_TXP PIE_TXP_MINIR PIE_RXN_LN PIE_RXP_LN 0 0.UF0V PIE_TXN PIE_TXN_LN 0 0.UF0V PIE_TXP PIE_TXP_LN PIE_RXN_US PIE_RXP_US 0 0.UF0V PIE_TXN PIE_TXN_ 0 0.UF0V PIE_TXP PIE_TXP_ If disable Port0,all PIE port will be disable. J0 SIE SIE WTO_ON_P SM G UF0V 0 PF0V 0 PF0V ER R.KOhm T TPT R R 0.UF0V 0 0.UF0V R R 0.UF0V 0.UF0V R0 R 0.UF0V 0.UF0V R R 0.UF0V 0.UF0V.KHZ X0 _PIE_S# _PIE_S LK MHZ has a ohm resistor near clk Gen. MI_OMP +V_RT RT power. For Rechargeable solution: Mount R T0 TPT R.Ohm R 0MOhm 0 TW R UF.V R R P P0 T T0 T T T T U U V V0 V V K K J J M M K K L L L M P P N N H J W W U00 MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP MI_ZOMP MI_IROMP MI_LKN MI_LKP T0 TPT 0.UFV R 0KOhm UF.V USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP O0# O# O# O# O# O#GPIO O#GPIO0 O#GPIO USRIS USRIS# LK LRQ0 LP Mmaster request,ihm has internal PU, but we need TPT datasheet H H H H J J K K K K L L M M N N E E G G F US INT P K USRIS_PN R Ohm 0PF0V RTRST# Place Near back oor SL0 SGL_JUMP.Ohm % R LK_US US_PN0 US_PP0 US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP ST RX,TX all need couple and place near onnector side for signal quality.nd Traces to them should match length. IHM need pull down RX, if no use. Z_LK_U Z_RST#_U Z_SIN0_U Z_SOUT_U Z_SYN_U RN0 0KOhm RN0 0KOhm RN0 0KOhm 0KOhm 0KOhm RN0 0KOhm 0KOhm 0KOhm L[0:] INT PU 0K +VSUS Place within 00 mils of IH US0 US US US US US US US US ONN US ONN US ONN lue tooth ard Reader amera N N R R R R R0 T0 TP PM_PWROK SYS_RESET# PR +VSUS RSMRST# Z_LK Z_RST# T0 T0 Z_SOUT Z_SYN IH_LNRST VRM_PWRG LRQ# X_RT X_RT RTRST# SMLERT# SMLLERT# SMLINK0 SMLINK RT well input requires pull down to reduce leakage from coin cell battery in G. ann't float in G. 0, 0, 0, 0, 0, LP_0 LP_ LP_ LP_ LP_FRME#, SL_, S M_S Int PU K Intel EMO reserved pull-up and pull-down,but no explaintion, so will check with Intel 0PF0V Reserved as intel demo sck. 0PF0V OHM OHM OHM OHM R 0KOHM % R0 KOhm R MOhm T T T T T T R MOhm 0PF0V V Y W Y Y P U W V P Y U E T V T P W T U W V T E0 H E H F F R T M P R 0PF0V U00 LRQ#GPIO L0FWH0 LFWH LFWH LFWH LRQ0# FWHLFRME# H_IT_LK H_RST# H_SI0 H_SIN H_SIN H_SOUT H_SYN LK EE_S EE_IN EE_OUT EE_SHLK LN_LK LNR_STSYN LN_RST# LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX RTX RTX RTRST# SMLERT#GPIO SMLK SMT LINKLERT# SMLINK0 SMLINK SPI_MISO SPI_MOSI SPI_S# SPI_LK SPI_R Z_LK PR p to 0p for EMI MI_STRP MI strap. UF_PLT_RST# 0 GI0 R US_SMI# GPIO US_SMI# R ER GPU_PWR_EN# 0,0 GPO R0 ER EXTSMI# GPU_HOL_RST# 0,0 RSMRST# P_I EXTSMI# 0 PM_RSMRST# 0 R WLN_ON# O_K_SI# WLN_ON# 0 ohm for debugging later. WIFI_SW# O_K_SI# 0 H_ON WIFI_SW# GPI R +VSUS GPU_PRSNT# 0 PM_PRSLPVR,0 EXTSMI# STP_PI# 0KOhm RN0 R GPI EHISEL#_PH STP_PU# WLN_ON# 0KOhm RN0 R EHISEL#_PH MI_STRP SMLERT# 0KOhm RN0 GPIO 0KOhm RN0 R R F_I HMI_ET_IN 0, ER O_K_SI# US_HRGE_ON F_I WIFI_SW# 0KOhm RN0 T LKRUN# H_ON 0KOhm RN0 T_ON 0KOhm RN0 WLN_LE T_ON, 0KOhm RN0 P_I WLN_LE +VSUS GPIO R ER GPU_PWROK,0,,,0 GPI R 00KOhm THERML_LERT# MHSYN IH_RI_PU PM_PWRTN# 0 T0 T0 INTRUER# RSMRST# INTVRMEN SPKR PRSTP# PSLP# TP =MI interface is strapped to operate in coupled mode. 0=MI interface is straped to operate in coupled mode. 0 0PF0V M_USY#GPIO0 GPIO GPIO GPIO GPIO GPIO0 GPIO GPIO GPIO GPIO PRSLPVR STP_PI# STP_PU# GPIO GPIO GPIO GPIO GPIO LKRUN# GPIO GPIO GPIO GPIO PUPWRGGPIO THRM# VRMPWRG MH_SYN# PWRTN# RI# SUS_STT#LPP# SUSLK SYS_RESET# PLTRST# WKE# INTRUER# PWROK RSMRST# INTVRMEN SPKR SLP_S# SLP_S# SLP_S# TLOW# PRSTP# PSLP# RSV R T W W K H M P E 0 Y R 0 F U V E H G G G T U0 J H0 E F F0 R0 R0 00KOhm T0 P_I0 SMI H_PWRG, VRM_PWRG 0,0 SYS_RESET#, UF_PLT_RST# 0,,,,,0 PIE_WKE#, PM_PWROK,0 PM_SUS# 0 PM_SUS# 0 PM_TLOW# 0 0KOhm KOhm P_I P_I P_I0 U0 IN IN +VSUS +VS V OUTY LVG0GW uffer for PLTRST# signal lready 0K pull up to +VS in clk gen section. R0 0KOhm R0 0KOhm +VSUS R0 0,0 0,0 R0 0KOhm R0 0KOhm 0,0 0, 0GTE F_SERIRQ R0 0KOhm O_KRST# ST_LE# SPLTRST#, PRSTP# PSLP# GPO GPIO GPIO SPKR STP_PI# STP_PU# WLN_LE MHSYN LKRUN# P_IO 0:dGPU :Optimus ER R 0KOhm R0 00KOhm SMLLERT# SMLINK0 SMLINK IH_RI_PU PM_PWRTN# PM_TLOW# SYS_RESET# PIE_WKE# THERML_LERT# GI0 INTVRMEN INTRUER# SUSTek omputer IN. +VP PM_PRSTP# PM_PSLP# +VS +VS +V_RT ustom R R R0 R R R R0 R R R0 PILK Run,if no use must PU! R R R Ohm R Ohm 0KOhm ER To PU and Vcore controller To PU. 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm 0KOhm KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 MOhm MOhm PH_IEX()_FI,MI,SYS PWR riesjesse Monday, May, 00 ate: Sheet of.0

23 SUSTeK OMPUTER IN. N PH_IEX()_P,LVS,RT *** Monday, May, 00 ate: Sheet of.00

24 PH_IEX()_PI,NVRM,US SUSTeK OMPUTER IN. N *** Monday, May, 00 ate: Sheet of.00

25 SUSTeK OMPUTER IN. N PH_IEX()PU,GPIO,MIS, H_Lin UL0 Monday, May, 00 ate: Sheet of.00

26 PH_IEX()_POWER, SUSTeK OMPUTER IN. N *** Monday, May, 00 ate: Sheet of.00

27 +VS +VS +VSUS +VSUS U00E VREF VREF_SUS VSTPLL VRT VMIPLL VUSPLL V_PU_IO V V V V V_0_ V_0_ V_0_ V_0_ V V V V V V VSUS VSUS VSUS VSUS F F Y E Y F W M M0 N J0 K P V0 H F0 G0 R0 T F N K F IH_VREF IH_VREF_SUS +VP +VP +V. +.VS +V.SUS 0 TW R0 0 T0 TPT 0 0.UF0V TW 0 0.UF0V +.V_ST_PLL 0.UF0V +V_RT V_0=0. V_ =. V_ =0. VccSUS_ =0.0 VccRT =u VREF =m VREF_SUS =0m V_PU_IO =m VUSPLL =0m VccMIPLL =m VccSTPLL=m R0 0.UF0V +VMI_PLL_IH +.VUSPLL 0UF.V +VSUS +V_RT +VS +V.SUS +VSUS R0 0 0.UF0V 0 0.UF0V 0 0.UF0V 0 0.UF0V +VS +V. R0 r00_h UF.V 0.UF0V 0.UF0V 0.UF0V 0.UF0V r00_h 0.UF0V 0.UF0V +VP Near F,K N,F U00F VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS 0 0 E F G G H H H K K K K K0 L M M N N N N N P P P R R T T V V V V V V W W Y Y 0 0 E E0 E 0 0UF.V 0 0.UF0V 0.UF0V 0.UF0V 0.UF0V VSS VSS VSS G E F +.VS +VMI_PLL_IH L0 00Mhz l UFV +.VS +.VS L0 0 0UF.V 0.UF0V 0.UF0V 00Mhz l00 0UF.V +.V_ST_PLL 0.UF0V +.VS L0 00Mhz l00 +.VUSPLL.UF.V RSV E SUSTek omputer IN. PH_IEX()_POWER, riesjesse ate: Monday, May, 00 Sheet of.0

28 PH SPI ROM SMUS Link device: No SPI FLSH TOOL ON +VSUS +VS SP, LKGEN, PU XP,PH XP, VI ONTROLLER, RVref +V R0 +V_SPI PH, SL_ R0.KOhm R0.KOhm Q0 UMKN +VS R0.KOhm R0.KOhm SM_LK_S,, 0 TW, S_ Q0 UMKN SM_T_S,, +V_SPI +V_SPI +V_SPI GPU_PWROK,0,,, SPI_S# O_SPI_O SPI_WP# SPI_O U0 S# V O HOL# WP# LK IO WX0VSSIG R0.KOhm R0 SPI_HOL# R0.KOhm SPI_LK 0 SPI_I 0 E,G0 R0 0 0PF0V UFV PF0V Q0 UMKN 0,0 SM_LK SM_LK_S SPI_I SPI_LK SPI_S# SPI_WP# 0 0PF0V 0 0PF0V 0 0PF0V 0 0PF0V 0,0 SM_T Q0 UMKN SM_T_S lose to OU SUSTeK OMPUTER IN. N PH_SPI ROM,OTH ustom riesjesse ate: Monday, May, 00 Sheet of.00

29 :isable 0:Enable PEREQ:PIEx0 & FS Function PIEx PEREQ:PIEx & FIXE PLL (synchronous) _LN_M PR PF0V PIEx & ST H PEREQ:PIEx & +VSUS +V_LK _ST_S PIEx & PIEx 0PF0V L0 00Mhz L PIPIEX PLL(synchronize) R0 MOhm _ST_S# 0PF0V l00 LK_PIE_US_PH 0PF0V +VS +V_LK_V LK_PIE_US#_PH 0PF0V X0.Mhz L0 00Mhz L0 00Mhz _XIN _XOUT _L_LVS# 0 0PF0V ER l00 0 l00 _L_LVS 0PF0V 0UF.V c00 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V PF0V PF0V STP_PI# 0PF0V for RF, STP_PU# 0 0PF0V close to pin +V_LK_V _PI_S_R 0 0PF0V +V_LK FS 0 0PF0V +V_LK U0 PR Ohm to Ohm S_ 0PF0V _LN_M R OHM _LN_M_R V MHzFREERUN SL_ STP_PI# PEREQ# PI&PIEX_STOP# 0PF0V 0 PEREQ# STP_PU# _REQ#_WLN PEREQ# PU_STOP# _FSL Ohm _O_REQ LK_REQ_WLN# R _M_S 0PF0V R0 FS PEREQ# REF0FSL Ohm _O_REQ LK_PEREQ# LK_EUG FSPILK0 O_PEREQ# R _FSL 0PF0V RN0 _XIN 0 _LP_E Ohm _PI_S_R VPI X 0 RN0 _XOUT _FSL ER _PI_S _M_R ITP_ENPILK_F0 X PF0V Ohm R0 LK_R_REER_ Ohm LK_EN SEL_#_MHz VREF R _M_R ER LK_US Ohm 0 Vtt_PwrGdP# ST 0 S_, PF0V SL_, R Ohm _FSL V SLK _LN_M_R _US0_M_R FSLUS_MHz 0PF0V PUT_LR0 LK_PU_LK _M_N LK_PU_LK# For RF,EMI OTT_MHzLR PU_LR0 _M_N# _FSL OT_MHzLR VPU FSL PUT_LR _FS_N _L_LVS PIeT_LR0 PU_LR 0 _FS_N# _RESET# +V_LK _L_LVS# PIe_LR0 RESET# R0 SYS_RESET#, 0 LK_PIE_PEG_PH PIeT_LR LK_PIE_PEG_PH_R 0 LK_PIE_PEG#_PH 0 PIe_LR V R _PIE_N _FSL VPIEX PUITPT_LRPIeT_LR R0 R H_ITP_LK 0KOhm R0 LK_PIE_US_PH PIeT_LR PUITP_LRPIe_LR H_ITP_LK# LK_PIE_PEG#_PH_R R LK_PIE_US#_PH.KOhm PIe_LR VPIEX R _PIE_N# LK_PIE_MINIR PIeT_LR PIeT_LR LK_PIE_LN LK_PIE_MINIR# PIe_LR PIe_LR LK_PIE_LN# 0 _ST_S STLKT_LR PIeT_LR _PIE_S 0 _ST_S# STLK_LR PIe_LR 0 _PIE_S# VPIEX +V_LK ISLPRSGLFT _FSL R.KOhm M_ STP_PU# R0 0KOhm ER _FSL R.KOhm _M_R R0.KOhm 0 O LK_PEREQ# +V_LK ER R.KOhm R KOHM % Q0 UMKN O 0 0 LK_EN# +VS R 0KOhm G Q0 N00 S 0 0.UFV _FSL R.KOhm 00M +V_LK _LN_M_R PR R.KOhm R0 LK_EN _O_REQ _REQ#_WLN PEREQ# _PI_S_R R R R R ER.KOhm.KOhm.KOhm.KOhm O_O O_O Voltage Status +V_LK R0 VP_OK_R# Q0 UMKN FS R0 +V_LK.KOhm L L H L H *.-.V 0.-.V 0-0.V Super Normal Power saving 0, VP_PWRG 0KOhm Q0 UMKN lock enable. R.KOhm % Q0 UMKN LK_EN R0 00KOhm R.KOhm FSL FSL FSL PU(MHZ) SUSTeK OMPUTER IN. N LK_ ISLPRSGLFT riesjesse ustom Monday, May, 00 ate: Sheet of.00

30 +V OU_P R00 VSUS_PWRG VSUS_PWRG 00 0UF.V c00 +V R0 0KOhm ER E_RSMRST# E_PWROK 00 0.UFV R00 R00 00 TW 00 TW 00 0.UFV +VSUS +VS 00 0.UFV R00.KOhm R00.KOhm 00 0.UFV PM_RSMRST# PM_PWROK,,,,,,0 0, 0,,0, UFV SM0_LK SM0_T SM_LK SM_T 00 0.UFV 0, F_SERIRQ, LP_FRME# _LP_E HG_FULL_LE#, LP_0, LP_, LP_, LP_ 0, O_KRST# O_K_SI# 0, 0GTE R00 S_PIRST# R0 UF_PLT_RST# O_P_LE# TP_LK TP_T T00 R00 0KOhm KSO[0..] KSI[0..], 0 0 E_LP_RST# 0 0.UFV US_HRGE_EN E_RST# KSO0 KSO KSO KSO KSO KSO KSO KSO KSO KSO KSO0 KSO KSO KSO KSO KSO KSI0 KSI KSI KSI KSI KSI KSI KSI NUM_LE# ER U00 SERIRQ LFRME# PILK LKRUN# L0 L L L KRST# SI# G0 PIRST# ERST# KSO0 KSO KSO KSO KSO KSO KSO KSO KSO KSO KSO0 KSO KSO KSO KSO KSO KSO KSO KSI0 KSI KSI KSI KSI KSI KSI KSI GPIO GPIO GPIO PSLK0 PST0 PSLK PST PSLK PST SL S SL S V V V V V V LP V IF V V 0 Key Matrix PWM0 Scan PWM PWM GPIO FN GPIO FNPWM0 FNPWM FNF0 FNF GPO GPO GPO 0 GPOE GPOF GPXIO00 GPXIO0 GPXIO0 00 XIOGPXIO0 GPXIO0 0 0 GPXIO0 GPXIO0 0 LE GPXIO0 0 0 GPXIO0 0 GPXIO0 0 GPXIO0 0 GPXIO PS 0 IF GPXIO0 0 GPXIO GPXIO XIO GPXIO GPXIO GPXIO GPXIO SM US GPXIO +V T_TS GPU_RST# OU_P O_SPI_WP# T_LERN 0 E_PWROK 0.UFV PU_LEVELOWN# THRO_PU +V_E T_TS R0 PM_PWRTN# FN0_PWM 0 FN0_TH 0 O G_KOFF# O PM_TLOW# SUS_ON,, VSUS_ON,, PU_VRON 0,, SUS_ON, PM_LEVELOWN# 0,,, HG_EN# PS-ON R0 SPI_WP# OP_S# 0 0UF.V c00 T00 ER PM_SUS# PM_SUS# VRM_PWRG,0 VSUS_PWRG +V.KOhm L00 00Mhz l00 L_L_PWM GPU_HOL_RST#,0 SPI_WP# 0, 0,,, 0, SM0_LK 0, SM0_T EXTSMI#, O_LI_E#, _OK 0,, PU_LEVELOWN PM_SUS# PM_SUS#,0 VRM_PWRG VSUS_PWRG, HG_FULL_LE# O_SPI_I O_SPI_LK_R O_SPI_S# SPI_WP# F_SERIRQ _LP_E 0, O_KRST# O_K_SI# 0, 0GTE S_PIRST# PM_PWRTN# G_KOFF# PM_TLOW# PM_LEVELOWN# HG_EN# +V T_IN HG_LE# O_PWR_LE_UP,, VSUS_ON 0,, PU_VRON OP_S# 0 0PF0V 0 0PF0V 0 0PF0V 00 0PF0V lose to S 0 +V +VS 0.UFV +V R0 R0 R00 R0 0KOhm 0KOhm 0KOhm 0KOhm 00KOhm 00KOhm 00KOhm 00KOhm.KOhm.KOhm.KOhm.KOhm RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 GPU_RST# GPU_PWR_ON#_E SM0_LK SM0_T SM_LK SM_T TP_LK TP_T T_IN _OK PM_SUS# PM_SUS#,0,,,,0, EXTSMI#, O_LI_E# GPU_PWR_EN# GPU_PWROK EPX_GTE_E# HMI_ET_IN, R0 ER R0 ER PWR_SW_E#, _OK Ohm R00 T_IN HG_LE# O_PWR_LE_UP R0 T00 EPX_GTE_IN# HOTKEY_SW# GPU_PWR_ON#_E GPU_PWROK_E E_RSMRST# LRT_E HMI_ET_IN_E 0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO GPIO0 GPIO GPI GPI GPIO0 GPIO GPIO GPIO GPIO K0QF SPI MISO 0 IF MOSI SPILK SPIS# 0 GPIO URT GPIO GPIO GPIO XLK XLKI XLKO VR Version: O_SPI_O O_SPI_I O_SPI_LK_R O_SPI_S# O_E_TX O_E_RX O_K_XLKI O_K_XLKO O_K_VR R0 R0 R0 0.UF.V T00 T00 SPI_I SPI_LK SPI_S# R00 0MOhm X00.KHZ O_SPI_O SPI_I SPI_LK SPI_S# ER 0 Q00 UMKN PU_LEVELOWN# 0 PF0V PF0V R0 KOhm PU_LEVELOWN 0,, LRT_E 00 0PF0V 00 0PF0V SM0_LK SM0_T 0KOhm R0 +V +V E_RST#_THERML R00 00KOHM 00 UF.V +V 00 NWS E_RST U00 N E_RST_I OUT V RNV-TR-F +V 0 0.UFV E_RST_I E_RST# Q00 UMKN THRO_PU H_PROHOT_S# T00 T_TS 0KOhm R0 T_LERN 0KOhm R0 HG_EN# VSUS_ON 0KOhm R0 0KOhm R0 E_RST R00 SUSTek omputer IN. riesjesse ustom E_ENE K0 Monday, May, 00 ate: Sheet of 0.0

31 For Keyboard onnector J0 SIE KSO KSO0 KSO KSO KSO 0 0 KSO KSO KSO KSO KSO0 KSO KSI KSI0 KSI KSI 0 0 KSI KSI KSI KSI KSO KSO KSO KSO KSO SIE KSO KSI KSI0 KSO KSO0 KSO KSI KSI KSI 0 0 PN0Y 0 PN0Y PN0Y KSI KSI KSO KSO KSI KSO FP_ON_P KSO 0 KSO 0 0 KSO[0..] KSI[0..] KSO KSO KSO0 PN0Y KSO 0 KSO KSO KSO PN0Y SUSTeK OMPUTER IN K riesjesse ate: Monday, May, 00 Sheet of.0

32 Thermal Policy +VSG R0 0KOhm +VS R.,item 0KOhm R0 VG_OT# PU_VG_THERM# R0 Q0 UMKN,0,,,,0 UF_PLT_RST# Q0 UMKN FORE_OFF# R0 R.,item E_RST#_THERML 0 R.,item Output Signal SUSTeK OMPUTER IN. N RST_Reset ircuit riesjesse ate: Monday, May, 00 Sheet of.0

33 PR change PN to 0G000 0 mil L0.UH LX 0.UFV +V_EN_LN_IO SL0 00 0UF.V _IO VT 0.UFV _IO PIE_TXN_LN_IO PIE_TXP_LN_IO LE0 +V_LN_IO _IO LX LE0 +VL +VL +VL LK_PIE_LN_IO LK_PIE_LN#_IO R0.KOhm _IO 0.UFV _IO place close to pin,0, UF_PLT_RST#_IO,0, PIE_WKE#_IO _IO UF0V _IO 0.UFV _IO +V_LN_IO VT_REG VT +VL X_LN 0.UFV X_LN +VH RIS UF0V _IO 0.UFV _IO R0.KOHM _IO U0 V PERSTn WKEn VT_REG VT VL_REG XTLO XTLI VH_REG 0 RIS R-L-R 0 LX LE[] LE[0] VL_REG RX_N RX_P VL REFLK_P REFLK_N TRXP0 TRXN0 N TRXP TRXN N N N N N 0 VL TX_P 0 TX_N N TESTMOE SMT SMLK VL LKREQn VH N +VL LK_REQ_LN +VH PIE_RXP_LN_IO_ 0.UFV PIE_RXN_LN_IO_ 0.UFV _IO T0 PIE_RXP_LN_IO PIE_RXN_LN_IO +VSUS_IO L0 00Mhz _IO +VL 0 mil 0 0UF.V +V_LN_IO 0 0 UF0V 0.UFV +VL +VH UF0V 0.UFV 0.UFV 0 close to pin _IO X_LN R0 0MOhm X0Mhz X_LN 0 0.UFV 0 0.UFV 0 0.UFV 0 UF0V 0.UFV 0.UFV 0.UFV 0.UFV PF0V _IO _LN_M_IO 0 PF0V PF0V _IO X_LN L_TRP0 L_TRN0 L_TRP L_TRN.OHM RN0.OHM RN0.OHM RN0.OHM RN0 0.UFV 0.UFV _IO _IO 0 close to pin _IO PWR_UTTON_LE SUSTEK OMPUTER IN nndy_wang ustom 00P_IO ate: Monday, May, 00 Sheet of.

34 +V_LN_IO L_TRP0 L_TRP 0 IP-Z L_TRN0 VIO VIO VUS VIO VIO L_TRN _LN_T 上上上上上上上上 _IO +V_EN_LN_IO 0 0 L_TRP0 L_TRN0 L_TRP L_TRN L_TRP0 L_TRN0 L_TRP L_TRN U0 R+ RX+ R- RX- RT RXT PTTTTXT T+ TX+ T- TX- 0 L_TRLP0 L_TRLN0 L_MT0 L_MT L_TRLP L_TRLN L_TRLP0 L_TRLN0 RN0 L_TRLP0_L L0 00Mhz L_TRLN0_L 0.UFV UF0V N N N N RN0 LFE _IO _IO L_TRLP RN0 L_TRLP_L L_TRLN L0 00Mhz L_TRLN_L 0.UFV 0 RN PFKV _LN_T LN IO RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm LN_ON LN_ON L_MT L_MT0 L_TRLN_L L_TRLP_L L_TRLN0_L L_TRLP0_L LN_P P_ P_ J0 0 _IO _IO Place near chassis LN IO SUSTEK OMPUTER IN PWR_UTTON_LE nndy_wang 00P_IO Monday, May, 00 ate: Sheet of.

35 LVS_L0P_PH LVS_L0N_PH Optimus RN0 Optimus RN0 LVS_L0P_ON LVS_L0N_ON LVS Switch LVS_LP_PH LVS_LN_PH LVS_LP_PH LVS_LN_PH Optimus RN0 Optimus RN0 Optimus RN0 Optimus RN0 LVS_LP_ON LVS_LN_ON LVS_LP_ON LVS_LN_ON LVS_LLKP_PH Optimus RN0 LVS_LLKP_ON LVS_LLKN_PH Optimus RN0 LVS_LLKN_ON LVS_L0P_ON LVS_L0N_ON LVS_LP_ON LVS_LN_ON LVS_LP_ON LVS_LN_ON LVS_LLKP_ON LVS_LLKN_ON LVS_L0P_GPU LVS_L0N_GPU LVS_LP_GPU LVS_LN_GPU +VS LVS_LP_GPU LVS_LN_GPU LVS_LLKP_GPU LVS_LLKN_GPU U0 0 0 V V 0 0.UF0V LVS_SW_SEL +VS LVS_L0P_PH LVS_L0N_PH LVS_LP_PH LVS_LN_PH R GPU_PWROK GPU LVS_LP_PH LVS_LN_PH LVS_LLKP_PH LVS_LLKN_PH GPU_PWROK,,0,,0 SEL=0 for 0 output(igpu) SEL= for output(gpu) +VS IN=0 for S output(igpu) IN= for S output(gpu) +VS +VS GPU GPU_PWROK R RT_RE_PH RE_GPU RT_RE RT_GREEN_PH GREEN_GPU RT_GREEN RG_SW_IN RT_LUE_PH LUE_GPU RT_LUE L_KEN_PH L_KEN_GPU L_KEN_ON L_VEN_PH L_V_EN_GPU L_VEN_ON RT_RE_PH Optimus RN0RT_RE RT_GREEN_PH Optimus RN0RT_GREEN RT_LUE_PH Optimus RN0RT_LUE Optimus RN0 RT_HSYN_PH RT_VSYN_PH L_KEN_PH L_VEN_PH Optimus Optimus Optimus Optimus RN0 RN0 RT_HSYN RT_VSYN RN0L_KEN_ON RN0L_VEN_ON +VS +VS GPU_PWROK _T_PH RT_T_GPU VG_T _LK_PH RT_LK_GPU VG_LK U0 RT SW_SEL S I0 I Y I0 I Y EI_LK_PH EI_LK_GPU LVS_EI_LK_ EI_T_PH EI_T_GPU LVS_EI_T_ 0 L_L_PWM L_PWM_GPU GPU_PWROK#_VS Q0 Q0 UMKN UMKN GPU GPU L_KLTTL_PH L_TL_PH L_KLTTL_ON R GPU_ LTL_GPU L_TL_GPU R Q GPU UMKN UMKN GPU_PWROK_VS Q GPU GPU Support dgpu boot mode => Use GPU_PWM_SELET# GPU_PWROK 0 0.UF0V GPU GPU V V V SEL V SM GPU V V 0 U0 IN V S EN# S S S S S S S 0 TSV0QR GPU 0 0.UF0V GPU U0 GPU_PWROK GPU RRT_SYN_SW_SEL S V RT_HSYN_PH I0 E# HSYN_GPU I I0 RT_HSYN Y I RT_VSYN_PH I0 Y VSYN_GPU I I0 RT_VSYN Y I 0 Y PIQE GPU 0 0.UF0V GPU GPU R PIQE GPU V E# I0 I Y I0 I 0 Y 0 0.UF0V GPU R 0KOhm GPU GPU_PWROK#_VS Q0 UMKN GPU R 00KOhm GPU GPU_PWROK_VS Q0 UMKN GPU L_KLTTL_PH R0 L_KLTTL_ON EI_LK_PH EI_T_PH _T_PH _LK_PH Optimus Optimus Optimus Optimus RN0 RN0 RN0 RN0 LVS_EI_LK_ LVS_EI_T_ VG_T VG_LK Optimus isplay Switch SUSTeK OMPUTER IN. N riesjesse ustom ate: Monday, May, 00 Sheet of.0

36 E R.L-V Issue P# is internal pull-up to VS_UIO & VIH=.V dd R0 &R of P# to make sure the P# is higher than.v when power up speaker amplifier V_IO +VS_MP_IO L0 +VS_IO +VS_IO +VS_UIO_IO esignip R. LY_OP_S# LY_OP_S#:"L" ==> P# = 0.V"H" ==> P# =.V EMI 00 +VS_IO _IO Z_MI_T_IO Z_MI_LK_IO Place R0 near U0 _UIO V USE 0 ohm00 0.UFV igital +VS_IO +.VS_IO 0 0.UFV, 0 R R Z_SIN0_U_IO +VS_IO JP0 SGL_JUMP JP0 +VS_IO V_IO Z_MI_T_IO_R Z_MI_LK_IO_R LY_OP_S#_R Z_SOUT_U_IO Z_LK_U_IO Z_SYN_U_IO Z_RST#_U_IO R 0KOhm _V R PMS0 _V_V 0UF0V Q0 SGL_JUMP _V R 0KOhm _V R0 Z_SIN0_U_IO_R Ohm T0 P_EEP TPT LY_OP_S#_R _IO 0 0.UFV _IO EP U0 _IO 0UF0V V GPIO0MI_T GPIOMI_LK P# ST_OUT LK VSS ST_IN V_IO SYN RESET# PEEP LQ-V-GR +VS_MP_IO 0UF0V _IO H_SPKR+ H_SPKR- H_SPKL- H_SPKL+ SPIFO EPSPIFO PV SPK_OUT_R+ SPK_OUT_R- PVSS PVSS SPK_OUT_L- 0 SPK_OUT_L+ PV V VSS Sense LINE_L LINE_R MI_L MI_R Sense JREF MONO_OUT MI_L MI_R LINE_L LINE_R 0 0 UF0V _IO 0 0.UFV 0.UFV P N PVEE HPOUT_R HPOUT_L PVREF MI_VREFO_R 0 MI_VREFO MI_VREFO_L VREF VSS V 00Mhz H_SPKR+ H_SPKR- H_SPKL- H_SPKL+ +VS_UIO_IO 0 0.UFV _UIO_IO PVEE MI_VREFOUT_L MI_VREFOUT LO_P VREF_OE _IO _V :0G0000 _V :0G0000.UF0V.UF0V UF0V 0 0UF0V U0 LQ-V-GR _HP_R _HP_L _IO 0 Z0-0H.RF _HP_R _HP_L.UF0V R0 _V 0 UFV c00 T0 0 0UF0V +VS_IO _V _IO +VS_UIO_IO UPMT-00 Vref = 0.V _V R0 +VS_UIO_SENSE.KOHM UPMT-00 (PN:0G0000) Vout=0.*(+(.K0K) =.V 0 0.UFV U0 EN NSSF VIN VOUT R R. o-lay for _V MI_VREFOUT_L _V 00PF0V R0 0KOhm % _V _V % _UIO_IO R0 R _V 0 UFV c00 _V _V +VS_UIO_IO MI_VREFOUT_L _UIO_IO For VI VT0P hange to.uf0v (PN:G0) Z_MI_T_IO R MI_VREFOUT Z_MI_T_IO_R MI_J LINE_J _UIO_IO For VI VT0P R0 hange to.kohm (PN:0G000) R0 R0 R0 UF0V T0 % 0KOhm %.KOhm _V UF0V c00 UF0V c00 R0 _UIO_IO % INTMI_L INTMI_R 0KOhm 00PF0V JREF MONO_OUT EMI 00 For VI VT0P hange to 0.uF (PN :G00) 0 may improve the audio performance _UIO_IO RealTek recommend change from.uf to uf New project : Please use the uf for VREF_OE On going project: Please keep.uf for VREF_OE if speaker have not S S resume issue. For EMI LO_P R0 MI_VREFOUT_L _V 0UF0V _UIO_IO _V EMI 0 R R R0 MI_IN E TPT.UF0V.UF0V MI_IN E_L MI_IN E_R R EMI 0 Z_LK_U_IO Z_MI_LK_IO_R 0 00PF0V R 0PF0V 0.UFV EMI _IO _UIO_IO _IO 0 remove P beep _IO For VI VT0P Please reserve G0000 for Z_LK_U at PH (S) side SUSTEK OMPUTER IN L- nndy_wang 00P_IO Monday, May, 00 ate: Sheet of.

37 E MI_VREFOUT_L HP & Mic. 0 Ext MI MI_IN E 0UF0V _UIO_IO R0.KOhm MI_J L0 00Mhz MI_J_ON R0 L0 MI_IN E MI_IN E KOhm ES 00Mhz 0 0PF0V 0 0PF0V 0 0PF0V 0 00PF0V J0 PHONE_JK_P G00M _UIO_IO _UIO_IO _UIO_IO _UIO_IO _HP_L R0 Ohm _HP_L_ON L0 00Mhz HP JK _HP_R R0 Ohm PR EMI ES +-K pass K 0 K 0 _HP_R_ON L0 LINE_J 00Mhz L0 00Mhz LINE_J Earphones Jack In : Low LINE_J_ON _HP_R_ON_L _HP_L_ON_L J0 _UIO_IO losed TO ONN 0 PHONE_JK_P 000PF0V 00PF0V 00PF0V 0PF0V _UIO_IO _UIO_IO _UIO_IO _UIO_IO INT SPK H_SPKR+ H_SPKR- H_SPKR+ H_SPKR- SL0 SL UF0V H_SPKR+_ON H_SPKR-_ON J0 SIE SIE FOR EMI E 0 0.UF0V FOR EMI 0 0.UF0V 000PFV 0 000PFV Wto_ON_P _IO H_SPKL+ H_SPKL- H_SPKL+ H_SPKL- SL0 SL _IO UF0V _IO H_SPKL+_ON H_SPKL-_ON _IO 0.UFV EMI 0.UFV EMI 0.UFV EMI 0.UF0V 0.UF0V 0 000PFV 0 000PFV _UIO_IO _IO _IO 0-0 Reserve for VI VT0P FOR IH Z US =.V +.VS_IO MUTE ONTROL R0 0KOhm +VS_IO Q0 PMS0 +VS_IO EP OP_S#_IO FROM E FOR IH Z US =.V 0, Z_RST#_U_IO R0 00KOhm FROM OE TW R0 Reserve for VI VT0P 0 LY_OP_S# LY_OP_S# TW dd EP to avoid POP noise when system into S S R0 00KOhm SUSTEK OMPUTER IN L- (IO) nndy_wang ustom 00P_IO Monday, May, 00 ate: Sheet of.

38 amera Module & Mic. +VS +VS R0 and R0 depend on MOS module support. 0 PF0V 0 ER R0 R0 ER 0 lose to J0 +VSUS US_PN US_PP +VS ER R0 0UF.V 0OHM RN0 00Mhz L0 0OHM RN0 +VS_MI 0 0.UFV US_PP_R US_PN_R +VS_MOS +VS_MI MI_LK_R MI_T_R ER +VS_MOS US_PN_R US_PP_R J0 SIE 0 SIE G0000 WTO_ON_P US_PP_R VIO US_PN_R VIO VUS VIO VIO MI_LK 0 IP-Z MI_T Int MI PR for VX EMI MI_LK MI_LK SL0 MI_LK_R MI_LK_R MI_T_R MI_T MI_T SHORT_PIN shortpin_r00 SL0 SHORT_PIN shortpin_r00 MI_T_R PF0V PF0V SUSTeK OMPUTER IN IO_SPK,INT MI,MOS riesjesse ate: Monday, May, 00 Sheet of.0

39 SUSTeK OMPUTER IN IO_US.0_*** riesjesse Monday, May, 00 ate: Sheet of.0

40 ,, PIE_RXP_US_IO PIE_RXN_US_IO INTROMEN SMI IO SEL PESEL PEPWRET PELKREQ# SPI_LK_IO R0 SPI_O_IO R0 SPI_S IO R0 SPI_I_IO R0 T00 T00 PORST# INTROMEN SMI IO PESEL PEPWRET PELKREQ# SEL TEST_EN +VSUS_IO R00.KOhm EHISEL# PEREXT EHISEL# US_S SPI_LK_IO_S US_S SPI_O_IO_S US_S SPI_S IO_S US_S SPI_I_IO_S URT_RX URT_TX HW Strip US_S 0 0 _IO R0 R0 R0 R0 US_S 0.UFV PIE_RXP_US_IO_ 0.UFV PIE_RXN_US_IO_ US_S _IO _IO +.V, LK_PIE_US_PH_IO PIE_TXN IO_S R0 US_S PIE_TXP IO_S PIE_TXN IO,, LK_PIE_US#_PH_IO R00 US_S PIE_TXP IO,, PIE_RXP_US_IO XI_S R0, PIE_RXN_US_IO US_S XI, PIE_TXP IO XO_S R0 US_S XO, PIE_TXN IO LK_PIE_US#_PH_IO_S R0 US_S LK_PIE_US_PH_IO_S LK_PIE_US#_PH_IO,,, PIE_WKE#_IO R0 US_S +V_U LK_PIE_US_PH_IO,,, UF_PLT_RST#_IO, SMI IO R0 US_S EHISEL# VU VU +VSUS_IO +.V R0 US_S VSUS_V VSUS_V TEST_EN IO_UF_PLT_RST# U_O U_O U_PPON U_PPON PIE_WKE#_IO R0 _UP_S _UN_S _UP_S _UN_S.KOhm US_S.KOhm INTROMEN=; External ROM.KOhm SMI# connect to S's SMI#_input.KOhm R0.KOhm R0.KOhm US_S R0.KOhm R0.KOhm R0.KOhm US_S SEL=0;0Mhz osc R0.KOhm TEST_EN=0; Normal=l R00.KOhm US_S R00 R0 0 U00 GPIO[] SMI# GPIO[] PE_SEL PE_PWRET PE_LKREQ# V_ SPI_LK SPI_O SPI_S# SPI_I PORST# URT_RX URT_TX V_ SM0.KOhm.KOhm GPIO[0] V_ PE_REXT VP 0 PE_TXN PE_TXP PE_RXN PE_RXP VP XI XO PE_LKN US_S PE_LKP 0 V_ UN_ UP_ VSUS_ VSUS_ UN_ UP_ VSUS_ PE_WKE# PPON_ PPON_ OI_# OI_# PE_RST# TEST_EN V_ V_ 0 0 VU_ URXN_ URXP_ UTXN_ UTXP_ UREXT VU UTXN_ 0 UTXP_ URXN_ URXP_ VU_ VSUS_ EHISEL=0;EHI mode connect to S's GPO by IOS control for EHI mode VU _URXN_S _URXP_S _UTXN_S _UTXP_S UREXT VU _UTXN_S _UTXP_S _URXN_S _URXP_S VU R00 R00 R0 R00 _URXN_ 0 0.UFV US_S _URXP_ 0 0.UFV US_S _UTXN_ 0 0.UFV US_S _UTXP_ 0 0.UFV US_S _UTXN_ 0 0.UFV US_S _UTXP_ 0 0.UFV US_S _UP UN_ US_PN_IO US_PP_IO _UP UN_ UFV 0.UFV +VSUS_IO +V_U US_S US_S US_S US_S 0KOhm US_S R0 R0 US_S R0 US_S R0 US_S US_S +.VS_P _UP UN UP UN URXN URXP_ +.VSUS_P +.VS_P PR US_S US_S _UP UN UP UN_ S US.0_NE_MHZ_G00000 NP0 0 XI_R S US.0_NE_MHZ_G00000 NP0 _IO R0 00KOhm US_S R00 00KOhm US_S RN0 0OHM RN0 0OHM RN0 0OHM RN0 0OHM 00Mhz L00 00Mhz L00 L00 00Mhz RN00 0OHM RN00 0OHM PF0V US US US US PF0V 0 U_PPON U_PPON U_O U_O UREXT PEREXT _UP_R _UN_R _UP_R _UN_R X00 0MHZ US.0_NE_0G0000 R0 NE R0.KOhm US_S R0.KOhm US_S XO _URXN_R _URXP_R _UTXN_R _UTXP_R _URXN_R _URXP_R _UTXN_R _UTXP_R R0 NE 0 PF0V S XI R0 NE % % _IO _IO _IO US_ES US_M_IO coxtl-sne U00 TMS_H- TMS_H+ TMS_H- TMS_H+ TMS_H- TMS_H+ TMS_H- TMS_H+ IPZ0-T U00 IPZ0-T N N N N N N N N N N 0 0 _IO _URXN_R _URXP_R _UTXN_R _UTXP_R _URXN_R _URXP_R _UTXN_R _UTXP_R IO_UF_PLT_RST# SPI_S IO SPI_I_IO WP#_ +V_U 00 0.UFV US_S _IO R0.KOhm US.0 NE_.KOhm +V_U _IO S# V SO HOL# SPI_LK_IO WP# SK SPI_O_IO SI HOL#- MXLM-G 0:Operation Lock :Normal Operation 00 UF_PLT_RST#_IO NWS US_S +V_US_IO F00 U_PPON PR PR _IO +V_US_IO F00 U_PPON _IO SPI ROM R0.KOhm US.0 NE_.KOhm R0.KOhm US_S 0G00 0G00 U00 cospi-sne.v.v U0 IN IN EN OUT OUT OUT O# TPS0GNG U0 IN IN EN OUT OUT OUT O# TPS0GNG 0G0000 0G00000 PSS0 PORST# R0 0KOhm 00 0.UFV _IO _IO 0 UF0V U_O U_O +V_U _IO R0.KOhm R00 R0 US_SUS +.VSUS_P_PWRG PG_V_P_IO US_VS colay-reset & POK R0.KOhm R0.KOhm R0.KOhm R0.KOhm _IO + _IO + _IO 0 00UF.V 00 00UF.V _IO _IO +V_US 0 0.UFV +V_US 0 0.UFV US_PN_IO US_PP_IO RN00 0OHM RN00 0OHM L00 00Mhz _IO _IO _IO +V_US_IO +.V +.VS_P +V_U VSUS_V VSUS_V UF.V 0.UFV 0.UFV 0.UFV US_S US_S US_S US_S _IO +.VS_P R0 00 type +V_U R0 00 type US_S UF.V 0.UFV 0.UFV 0.UFV US_S US_S US_S US_S _IO US_S VU lose to SM UFV 0UF.V US_S US_S UF.V 0.UFV 0.UFV US_S US_S US_S _IO _IO _IO VU _IO UFV 0.UFV 0.UFV 0.UFV US_S US_S US_S US_S _URXN URXP UTXN UTXP URXN URXP UTXN UTXP URXN URXP UTXN UTXP URXN URXP UTXN UTXP_ L00 00Mhz RN00US RN00US RN00 US RN00 US L00 00Mhz RN00 US RN00 US L00 00Mhz L00 00Mhz RN00 US RN00 US _URXN_R _URXP_R _UTXN_R _UTXP_R _URXN_R _URXP_R _UTXN_R _UTXP_R _UN_R _UP_R VIO VIO +V_US _UN_R VUS VIO VIO 00 IP-Z _UP_R _IO coes-sne +V_US _UN_R _UP_R _URXN_R _URXP_R _UTXN_R _UTXP_R _IO +V_US _UN_R _UP_R _URXN_R _URXP_R _UTXN_R _UTXP_R _IO J00 VUS - + P SSRX- SSRX+ SSTX- SSTX+ 0 P_ P_ SIE SIE US_ON_XP N J00 VUS - + P SSRX- SSRX+ SSTX- SSTX+ 0 P_ P_ SIE SIE US_ON_XP N US.0:G000R EMI _IO _IO 0 0.UFV EMI riesjesse SUSTeK OMPUTER IN 0 0.UFV US_Port Monday, May, 00 ate: Sheet of 0.0

41 SUSTeK OMPUTER IN Jerry Yu UL0 ate: Monday, May, 00 Sheet of.

42 廠廠廠廠廠 0.UF HIPRESETN +VS SL UF0V US_PP US_PN Max : 0. +V_R 0 0.UF0V RN0 0OHM US_PP_R L0 00Mhz 0OHM US_PN_R RN0 Max: 00m +V_R 0 0.UF0V +.V_R SLKXLEMSS LK_R_REER_ 0.UF0V +V_R SLKXLEMSS 0.UF0V 廠廠廠廠廠.UF EMI dvice Place Near onnector PF0V 0 R0 +V_R HIPRESETN US_PP_R US_PN_R +V_R T_S T_S T_S SMXRN R0 N SLKXLEMSS_R UF.V 0 UF.V R0 Ohm T0_S T_S +V_R Output 0 U0 EXTIN HIPRESETN REXT VP P M VSP VU F_V V TRL XN XEN ST U-GLF-GR J0 ST TRL TRL T T0 T T TRL0 T 0 TRL T T T XWPN P_ P_ 0 S_SOKET_P G R0 Ohm T0_S R0 SLKXLEMSS Ohm SMXRN T_S SWPXLEMSLK SNXWRN T_S SWPXLEMSLK SNXWRN SWP: Internal Pull-up SN: Internal Pull-up SWP = Write protect SWP = 0 Write-able SN = No card SN = 0 ard inserted 0 0PF0V 000 EMI dvice Place Near U00 0PF0V 0 0PF0V 0.UF0V EMI 0 SUSTeK OMPUTER IN Title R : REER U riesjesse ate: Monday, May, 00 Sheet of.0

43 SUSTeK OMPUTER IN EXPRESS R ONN Jerry Yu UL0 ate: Monday, May, 00 Sheet of.

44 LP EUG PORT LP ebug Port +VS 0 0.UFV EUG,0 LP_0,0 LP_,0 LP_,0 LP_,0 LP_FRME# LK_EUG LP_0 LP_ LP_ LP_ LP_FRME# LK_EUG 0 J0 SIE 0 SIE FP_ON_P EUG SM G0 +VP J0 +VP H_PMN_REQ# PM# H_PMN_REQ# H_PMN_RY# H_PMN_ PM# PM# H_PMN_RY# H_PMN_ PM# H_PMN_ R0 H_PWRG_R, H_PWRG XP KOhm PM# 0 H_PMN_0 R0 XP Ohm TESTIN# PWRGOO PM0# RESERVE VTT LK0 H_ITP_LK GLKp KL H_ITP_LK# GLKn 0 PURST_ITP# RESET# R0 XP KOhm,, SM_LK_S SL R# SYS_RESET#,,, SM_T_S S TO H_TO TRST# H_TRST# N H_TK 0 TK TI H_TI TMS H_TMS +VP NP_N NP_N TO_ON_P SPLTRST#, 0 0.UFV XP hange evice and P footprint of XP to nomask footprint - nomask solution XP 新 Layout 機機機 XP onnector 機請 G00 (w through holes) SUSTeK OMPUTER IN UG EUG PORT riesjesse ustom ate: Monday, May, 00 Sheet of.0

45 0OHM RN0 0OHM RN0 HMI ON. HMI_TXP0 HMI_TXN0 HMI_TXP HMI_TXN HMI_TXP HMI_TXN HMI_LKP HMI_LKN +VS 0.UF0V 0.UF0V R0 OHM R0 OHM R0 OHM R0 OHM R0 OHM R0 OHM R0 OHM R0 OHM Q0 N00 +VSG G S R 00KOhm 0 0.UF0V 0 0.UF0V 0 0.UF0V 0 0.UF0V 0 0.UF0V 0 0.UF0V +VS_HMI_L +VS_HMI 0 F0 0 mil SS00 ER.V JP0 MM_OPEN_MIL 0 0.UFV HMI_TX0P_ HMI_TX0N_ HMI_TXP_ HMI_TXN_ HMI_TXP_ HMI_TXN_ HMI_LKP_ HMI_LKN_,,0,,0 GPU_PWROK HMI_TX0P_ HMI_TX0N_ HMI_TXP_ HMI_TXN_ HMI_TXP_ HMI_TXN_ HMI_LKP_ HMI_LKN_ L 00Mhz HMI_TX0P_ON HMI_TX0N_ON HMI_TXP_ON HMI_TXN_ON HMI_TXP_ON HMI_TXN_ON HMI_LKP_ON HMI_LKN_ON +VS_HMI HMI_TXP_ON HMI_TXN_ON HMI_TXP_ON HMI_TXN_ON HMI_TX0P_ON HMI_TX0N_ON HMI_LKP_ON HMI_LKN_ON HMI_TX0P_ON HMI_TX0N_ON HMI_LKN_ON HMI_LKP_ON HMI_TXP_ON HMI_TXN_ON HMI_TXP_ON HMI_TXN_ON HMI_LK_ HMI_T_ +VS_HMI HMI_HP_ U Line- Line- Line- Line- Z0-0F ER N N N N ER G0X HMI_TX0P_ON HMI_TX0N_ON HMI_LKN_ON HMI_LKP_ON HMI_TXP_ON HMI_TXN_ON HMI_TXP_ON HMI_TXN_ON HMI_LK_GPU HMI_LK_ GPU_PWROK 00Mhz L0 0OHM RN0 0OHM RN0 L0 00Mhz 0OHM RN 0OHM RN 0OHM RN 0OHM RN L 00Mhz RN0.KOhm U0 UMKN RN0.KOhm U Line- Line- Line- Line- Z0-0F N N N N J0 0 0 P_ P_ P_ P_ HMI_ON_P 0 0 PF0V R MOhm HMI_T_GPU U0 UMKN HMI_T_ 0 PF0V HMI_HP_VG 0 TW HMI_ET_IN,0 HMI_ET_IN HMI_ET_IN R0 HMI_HP_ KOhm R 00KOhm +VS_HMI 0 V SUSTeK OMPUTER IN. N HMI_ONN riesjesse ate: Monday, May, 00 Sheet of.00

46 +L_LEIN G000K J0 L_KLTTL_ON LVS_LLKP_ON LVS_LLKN_ON LVS_LP_ON LVS_LN_ON LVS_LP_ON LVS_LN_ON LVS_L0P_ON LVS_L0N_ON L_VEN_ON +VEI,0,,,,0 R L_KLTTL_ON_R LVS_LLKP_ON LVS_LLKN_ON LVS_LP_ON LVS_LN_ON LVS_LP_ON LVS_LN_ON LVS_L0P_ON LVS_L0N_ON L_EN R0 EITON EILKON O_LI_E# UF_PLT_RST# L_KEN_ON 0 G_KOFF# 0 TW 0 TW 0.UFV L_EN UF.V 0.UFV wtob_con_0p +VS_L R0 0KOhm +VS_L L0 EILKON 00Mhz L0 EITON 00Mhz +VS +VEI +VS_L R0 R0 PF0V +VS L_VEN_ON PR 0.UFV R MOhm LVS_EI_LK_ LVS_EI_T_ Q0 EMFP0J S ER G S 0 UF.V R0 00KOHM G Q0 lose to L onnector N UF.V 0.UFV PR Q0 UMKN R 0KOhm +V R0 00KOHM Q0 UMKN R0 +VS_L 0 0.UFV _T_SYS +L_LEIN R0 r00_h acklight Enable ischarge _T_SYS Q0 EMFP0J UF.V +V 0 V +V 0.UFV U0 V Output E--F +V R 00KOHM 0PF0V O_LI_E# 0, R0 00KOHM 0.UFV G S R0 00KOhm Q0 L_EN G N00 S UFV +L_LEIN 0.UFV SUSTek omputer IN. LVS onn riesjesse ustom ate: Monday, May, 00 Sheet of.0

47 Layout note: Near U0 J0 PLE ES iodes near connector +VS GREEN_ON RE_ON 0 VIO VIO LUE_ON IP-Z VUS VIO VIO HSYN RT_RE RT_GREEN RT_LUE R0 % R0 % L0 0.0uH 0 0PF0V c00 L0 0.0uH 0 0PF0V c00 L0 0 0PF0V c00 0 0PF0V c00 RE_ON GREEN_ON LUE_ON RE_ON GREEN_ON LUE_ON RE_RTN RE GREEN_RTN GREEN LUE_RTN LUE +V N 0 _SU_P P_ P_ G0V HSYN N S HSYN HSYN VSYN VSYN SL RT ON. +VS 0 V VSYN R0 % 0 0PF0V c00 0.0uH 0 0PF0V c00 VSYN +VS 0 0.UFV RT_VSYN U0 OE# V Y VSYN_RT RN0 OHM VSYN LVGGV 0 PF0V c00 +VS 0 +VS_RT RT_HSYN U0 0.UFV OE# V Y HSYN_RT RN0 OHM HSYN +VS NWS RN0.KOhm RN0.KOhm LVGGV 0 PF0V c00 Q0 UMKN Q0 UMKN VG_T VG_LK SUSTeK OMPUTER IN. RT_-SU riesjesse Monday, May, 00 ate: Sheet of.0

48 SUSTeK OMPUTER IN UL0 Jerry Yu ate: Monday, May, 00 Sheet of.

49 SUSTeK OMPUTER IN UL0 Jerry Yu ate: Monday, May, 00 Sheet of.

50 PU_THRM_ PU_THRM_ PF0V +V_THRM +VS L00 00Mhz l UFV,0 SM_LK,0 SM_T PF0V H_LERT# T00 PU_THRM# PU_THRM_ PU_THRM_ +VS FN ONN 0 FN0_TH +VS +V_R +VS PR RN00.KOhm FN_PWM FN_TH PR RN00.KOhm +VS ER SUSTeK OMPUTER IN FN THERML SENSOR FN ONN riesjesse 0 FN0_PWM 0PF0V U00 SMLK V SMT XP LERT# XN THERM# G0PU T00 RN00.KOhm R00.KOhm % 00 0UF.V.KOhm RN UFV Q00 PMS0 E 00 00PF0V 00 00PF0V G0000 Wto_ON_P N N J00 ustom ate: Monday, May, 00 Sheet 0 of.0

51 0 ST_TXP0 0 ST_TXN0 0 ST_RXN0 0 ST_RXP0 ST H 0 0.0UFV 0 0.0UFV ST_H_TXN0 ST_H_TXP0 G000 J0 NP_N NP_N +VS 0 0.UFV 0 0UF.V +VS + 0 UF.V. 0 0UF.V 0 0.UFV +VS NP_N NP_N ST_ON_P SUSTeK OMPUTER IN X ST H ONN riesjesse ate: Monday, May, 00 Sheet of.0

52 +VSUS +VSUS +VSUS +VSUS_US_ON PJP0 F0 +VS MM_OPEN_MIL.V PJP0 MM_OPEN_MIL bom:0g00 +VSYS_US F V USHRGE US_PP0 US_PN0 +VSUS + +V_US_ON 0 UF.V U_INT# USHRGEX RN0 0OHM RN0 0OHM USHRGEX +V_US_ON 0 0UF.V USP0+_I USP0-_I UF.V USHRGEX R USHRGE QUSHRGE UMKN USHRGE R 0 0.UFV US_ON_XP VUS SIE - P_ + P_ SIE J0 Q UMKN USHRGE USP0-_I USP0+_I +VSUS L0 00Mhz RN0 0OHM RN0 0OHM o-layout for EMI USP0- USP0+ USP0- USP0+ US : M VIO VIO VUS VIO VIO 0 IP-Z R KOhm R KOhm USHRGE USHRGE 0.UFV U_US_SEL US_PP0 US_PN0 US_PP0 US_PN0 R KOhm USHRGE R KOhm USHRGE R USHRGE R USHRGEX R USHRGEX U_US_PE# U_US_MS U_US_SEL +VSUS R.KOhm USHRGEX R.KOhm USHRGEX R.KOhm USHRGEX MS:internal 00K pull-up; SEL:internal 00K pull-down USHRGE USHRGE+VSUS R.KOHM R.KOhm +VSUS R.KOhm T0 USHRGE UF.V USHRGEX PIUSZKEX U_INT# U + V INT 0 - M+ M- Y+ Y- SEL + - INT# N RESET# + - TEST OE# MS USHRGE 0 PE# V S# U_US_MS USP0-_I USP0+_I U_US_PE# U_US_S# +VSUS 0.0UFV USHRGE R KOhm USHRGE R.KOHM R0.KOHM USHRGE USHRGE R +VSUS USHRGE R 0KOhm USHRGE Q UMKN USHRGEGMTX R0 USHRGE +VSUS INPUT 0,, VSUS_ON US_HRGE_ON OUTPUT OE# MS PE# S# SEL INT X 0 0 Hi-Z Short X H uto PR 0, US_HRGE_EN R 0KOhm USHRGE USHRGE R TW USHRGE +VSYS_EN +V_US_ON ER R 0 USHRGEGMT US_PP0 US_PN0 U N N NO NO V 0 S OM OM OE G0REU USHRGEGMT R.KOhm USHRGEGMT % U_US_S# USP0+_I USP0-_I R 0KOhm USHRGEGMT USHRGEGMT R +V R0 0KOhm USHRGEGMTX Q UMKN +V_US_ON USHRGEGMTX R 0KOhm USHRGEGMTX SUSTeK OMPUTER IN US.0 ONN* riesjesse ustom ate: Monday, May, 00 Sheet of.0

53 +VUX_GOLN +.VS +VUX_GOLN, PIE_WKE# LK_REQ_WLN# R0 R0 LK_PIE_MINIR# LK_PIE_MINIR WLN_WKE# T_ON_L_0 J0 WKE# Reserved Reserved LKREQ# REFLK- REFLK+.V_.V_ UIM_PWR UIM_T 0 UIM_LK UIM_RESET UIM_VPP ER US_PN US_PP 00Mhz L0 RN0 0OHM RN0 0OHM USP- USP+ PIE_RXN_MINIR PIE_RXP_MINIR +VUX_GOLN PIE_TXN_MINIR PIE_TXP_MINIR ReservedUIM_ ReservedUIM_W_ISLE# PERST# PERn0 +.Vaux PERp0.V_ SM_LK PETn0 SM_T PETp0 0 US_- Reserved US_+ Reserved Reserved LE_WWN# Reserved LE_WLN# Reserved LE_WPN# Reserved.V_ Reserved Reserved0.V_ MINI_PI_LTH_P NP_N NP_N RF_EV_ON USP- USP+ UF_PLT_RST#,0,,,,0 T_ON_L_0 +VUX_GOLN R0 0KOhm 0 TW +VS T_ON, +VSUS 0.UFV +VS L0 00Mhz 0 0UF.V 0 0.UFV 0000 hange to G0000P 0 0.UFV +VUX_GOLN 0 0.UFV 0 0.0UFV +.VS 0 0UF.V 0 0.UFV +VUX_GOLN R0 00KOhm r00 Int. PU for Windigo 0 TW RF_EV_ON R0 0KOhm WLN_ON Q0 N00 WLN_ON S G WLN_ON# SUSTeK OMPUTER IN Title MINI-PIE : WLN ONN ustom riesjesse ate: Monday, May, 00 Sheet of.0

54 H0 N H0 OXOXN H0 N PWR SW R0 PWR_SW#_ON_PWR_R PWR_SW#_ON_PWR PWR_SW#_ON_PWR_R SW0 H0 NP_N Ohm 0 0.UFV TP_SWITH_P G000 N _PWR _PWR _PWR _PWR 00 revised hole For POWER ON LE +V_PWR R0 PWRON_LE+_PWR LE0 + PWRTN_LE_PWR PWRTN_LE_PWR % WHITE 0 000PF0V +V_PWR 0 0.UFV PWRON_LE+_PWR 0 0.UFV LE0 + WHITE LE0 0 update LE to add LE* (anderson) _PWR _PWR _PWR + 0 change white LE WHITE +V_PWR PWR_SW#_ON_PWR PWRTN_LE_PWR J0 SIE SIE WTO_ON_P SUSTEK OMPUTER IN PWR_UTTON_LE Shangyunderson _PWR _PWR VX_PWR_TN ate: Monday, May, 00 Sheet of.

55 PWR SW PWR_SW#_ON_IO PWR_SW#_ON_IO R0 Ohm N 0 0.UFV PWR_SW#_IO SW0 TP_SWITH_P G000 _IO N _IO For POWER ON LE +V_US_IO R0 % N 0 PWRON_LE+ + PWRTN_LE_IO LUE 0 update LE to 00 N +V_US_IO PWR_SW#_IO PWRTN_LE_IO _IO J0 SIE SIE WTO_ON_P VX _IO SUSTEK OMPUTER IN 00P_IO PWR_UTTON_LE nndy_wang ate: Monday, May, 00 Sheet of.

56 + Touch-Pad onn. RightLeft SW. +VS SL0 00 +V_TP 0 TP_LK 0 TP_T 0 PF0V 0 UFV 0 0.UFV N RIGHT LEFT 0 PF0V ER J0 SIE 0 0 SIE FP_ON_P LEFT G000 SW0 TP_SWITH_P N RIGHT SW0 TP_SWITH_P N G00 N For WLN LE For IEFLSH LE 0 EMI near TN for ES LUE N N WLN_LE WLN_LE Q0 UMKN LE0 ER +VS R0 WLN_LE+ + WLN_LE- % LEFT 0 O_PWR_LE_UP ER 0 0.UFV +VS LE0 R0 HG_LE# FLSH_LE+ + FLSH_LE- RIGHT F.FU % +VS N LUE N 0 0.UFV R0 FLSH_LE Q0 0 0KOhm UMKN RIGHT HG_FULL_LE# LEFT 0, ST_LE# Q0 UMKN PWR LE harge LE F.FU +VSUS For POWER LE ER LE0 For HRGE LE R0 PWR_LE+ LE0 + PWR_LE- PWR_LE- +VSUS ORNGE + HG_LE_ORNGE# R0 0, % N O_PWR_LE_UP LUE N O_PWR_LE_UP T0 Q0 UMKN + GREEN GREENORNGE 0G000 % N R0 HG_LE_GREEN# N % 0 HG_FULL_LE# O_HG_LE_GREEN# N 0 HG_LE# O_HG_LE_ORNGE# +VS +VS 0 UFV 0 0.UFV VX N R0 % TP_LK TP_T +VS +VSUS +VSUS 0 0 PF0V O_P_LE# PF0V WLN_LE- FLSH_LE- PWR_LE- O_HG_LE_GREEN# O_HG_LE_ORNGE# FP_ON_P 0 0 J0 VX N LE0 LUE O_P_LE# 0 LE PWR LE FO ONN riesjesse SUSTeK OMPUTER IN Monday, May, 00 ate: Sheet of.0

57 +.V R0 +V R0 00KOHM +.V_ISHRG Q0 UMKN +0.VS +.VS,0, SUS_ON Q0 UMKN +VP RN0 0OHM +.VS RN0 0OHM RN0 0OHM RN0 0OHM +V +VP_ISHRG +.VS_ISHRG +0.VS_ISHRG R0 00KOHM Q0 UMKN Q0 UMKN +.VS_ISHRG 0, SUS_ON G Q0 UMKN Q0 UMKN S Q0 N00 SUSTek omputer IN. ischarge riesjesse ustom.0 Monday, May, 00 ate: Sheet of

58 Touch-Pad onn. RightLeft SW. +VS_TP 00 revised T and LK SL UFV 0 0.UFV 0 G00 0 mirror vertically ER LEFT_TP FP_ON_P G000 RIGHT_TP TP_T_R_TP TP_LK_R_TP 0 PF0V _TP _TP _TP 0 PF0V LEFT_TP RIGHT_TP SIE 0 0 SIE ON0 SW0 TP_SWITH_P SW0 TP_SWITH_P _TP _TP _TP _TP For WLN LE For IEFLSH LE 0 EMI near TN for ES ER +VS_TP R0 LE0 WLN_LE+_TP WLN_LE-_TP % WHITE 00 change to white light ER +VS_TP R0 LE0 FLSH_LE+_TP FLSH_LE-_TP % WHITE 00 change to white light LEFT_TP _TP RIGHT_TP _TP 0 0.UFV 0 0.UFV _TP 0 PWR_LE-_TP O_HG_LE_ORNGE#_TP F.FU 0 RIGHT_TP O_HG_LE_GREEN#_TP LEFT_TP PWR LE +VSUS_TP For POWER LE ER harge LE For HRGE LE +VS_TP R0 % _TP F.FU R0 LE0 PWR_LE+_TP PWR_LE-_TP % WHITE 00 change to white light +VSUS_TP MERGREEN LE0 R0 HG_LE_ORNGE#_TP % R0 HG_LE_GREEN#_TP % O_HG_LE_GREEN#_TP WHITE LE0 O_P_LE#_TP 00 change to white light 00 change to ambergreen light O_HG_LE_ORNGE#_TP +VS_TP H0 H0 H0 NP_N NP_N NP_N 0 UFV 0 0.UFV N N N _TP _TP _TP _TP _TP _TP TP_LK_R_TP TP_T_R_TP 0 PF0V _TP _TP _TP 0 PF0V +VS_TP +VSUS_TP +VSUS_TP O_P_LE#_TP WLN_LE-_TP FLSH_LE-_TP PWR_LE-_TP O_HG_LE_GREEN#_TP O_HG_LE_ORNGE#_TP _TP FP_ON_P 0 0 J0 00 mirror vertically (anderson) 00 mirror vertically for positivenegative line _TP H0 H0 N OXOXN H0 NP_N TN _TP _TP 00 revised hole LE PWR LE FO ONN Shangyunderson SUSTeK OMPUTER IN VX_TP Monday, May, 00 ate: Sheet of.0

59 SUSTeK OMPUTER IN UL0 Jerry Yu ate: Monday, May, 00 Sheet of.

60 attery onnector G00000N TT_ON_P P_ T00 T00 T0 T0 T_ON T L00 00Mhz Irat= L00 00Mhz Irat= VIO VIO +V VUS VIO VIO PR 00 IP-Z P_ J00 ER 0 R00 R00 R UFV T0 T0 T0 T0 T0 T0 T0 00 PF0V 00 PF0V Recommand max PF, for Q0Z0 rising time spec. 00 PF0V SM0_LK 0, SM0_T 0, T_IN# Total count: pcs 0 -> 000:. hange 00 from F.FU to IP-Z for cost down and integration. SUSTeK OMPUTER IN. N _ & T IN riesjesse ustom ate: Monday, May, 00 Sheet 0 of.0

61 LUETOOTH ONNETOR R0 +VS US_PP US_PN L0 00Mhz R0 T_US_PP T_US_PN 0 0.UFV T0 T_Link_LE T_ON_L J0 SIE SIE WTO_ON_P G000 ER T_ON_L +VS R00 0KOhm To match WHQL test.ue to T wake up to spend much time if use +VS.So,change to +V,let T can work quickly when S wake up. 0 TW T_ON, SUSTeK OMPUTER IN ustom lue Tooth riesjesse ate: Monday, May, 00 Sheet of.0

62 SUSTeK OMPUTER IN UL0 TPM Jerry Yu ate: Monday, May, 00 Sheet of.

63 Express gate SW#_ON_EXP R0 VX Ohm SW0 H0 N H0 OXOXN H0 N SW#_ON_EXP TP_SWITH_P 0 00PF0V _EXP 0 PF0V _EXP _EXP H0 NP_N 0.0 revised Hole N SW#_ON_EXP J0 SIE _EXP _EXP SIE WTO_ON_P _EXP _EXP MO MOS MER SUSTeK OMPUTER IN VX_EXP Shangyunderson ate: Monday, May, 00 Sheet of.0

64 _T_SYS +VS +V _IO _IO +VS _T_SYS +V 0 0.UFV EMI EMI H0 SREW_HOLE 0 0.UFV EMI 0.UFV EMI H0 NP_N H0 OXOXN 0 0.UFV EMI 0 0.UFV EMI 0 0.UFV EMI 0.UFV N H0 0 EMI 0.UFV EMI 0.UFV _IO NP_N N H0 _IO IO card part 0 0.UFV EMI 0 0.UFV EMI 0 0.UFV EMI 0.UFV EMI 0.UFV EMI 0.UFV EMI 0.UFV EMI 0.UFV EMI +VP +0.VS_GMH NP_N +VS +VSUS +VS EMI 0.UFV +VSUS_US_ON _IO +.VSG N _IO 0 0.UFV 0.UFV 0.UFV 0.UFV EMI EMI EMI EMI +0.VS_GMH +0.VS_GMH +VSG 0 0.UFV EMI EMI 0.UFV EMI 0.UFV 0 0.UFV EMI +0.VSG +0.VSG +.VSG +VP +VORE EMI EMI 0.UFV 0.UFV 0.UFV EMI +V _T_SYS EMI 0.UFV +VSUS_US_ON 0.UFV EMI EMI 0.UFV +VS +VSUS EMI 0.UFV +VS +VS +V +VSUS EMI EMI 0.UFV +V +VS +V 0.UFV +VS 0 EMI EMI 0.UFV 0.UFV +V +VP +V +VORE EMI EMI 0.UFV 0.UFV SUSTeK OMPUTER IN EMI_P riesjesse ate: Monday, May, 00 Sheet of.0

65 H0 NP_N N s00 H NP_N N s00 H0 TRX H0 N mm E hole H OX0OX0N x.mm hole H N mm hole H HOLE_NPTH H HOLE_NPTH H HOLE_NPTH H HOLE_NPTH PU bracket hole H0 NP_N N s00 H0 H OXOXN H OXOXN.xmm hole H NP_N NP_N G0000 NUT RTXN s0 N s00 H0 NP_N H H H0 UF-M-EXPREE UF-M-EXPREE UF-M-EXPREE H NP_N RTXN s0 N s00 H0 TYPE SREW Hole NP_N N s00 H0 NP_N N s00 TYPE SREW Hole SUSTek omputer IN. Srew Hole riesjesse ate: Monday, May, 00 Sheet of.0

66 urrent setting= epend on the current of the adaptor. Jack +V_JK _OK_IN J0 P_ P_ P_ P_ NP_N _POWER_JK_P T0 T0 T0 T0 0 0.UFV L0 Irat= L0 Irat= 0 SS00 00Mhz 00Mhz 0 0UFV 0 UFV 0 0.UFV R00 KOhm G0 N T0 T0 T0 T0 +V_JK J0 P_ P_ P_ P_ NP_N _POWER_JK_P G0 VX SUSTeK OMPUTER IN RT_ ON riesjesse ustom ate: Monday, May, 00 Sheet of.0

67 +V_US_IO _IO +VS_IO _IO +VSUS_IO 0 0.UFV EMI _IO 00PF0V XEMI 0.UFV lose to U_ON Z_MI_LK_IO 0 0.UFV 0 0.UFV +VSUS_IO _IO +.VS_IO _IO +VS_IO 0 0.UFV _IO 0.UFV EMI 0.UFV EMI _IO 0 0.UFV 0 UF0V +.VS_IO +VS_IO +VSUS_IO +VSUS_IO +VS_IO PR 0 0 VSUS_ON_IO 0 US_PP_IO 0 US_PN_IO PR LK_PIE_LN_IO LK_PIE_LN#_IO PWRTN_LE_IO,,0 PIE_WKE#_IO,,0 UF_PLT_RST#_IO PWR_SW#_IO +V_US_IO 0 EHISEL# PIE_TXN_LN_IO PIE_TXP_LN_IO PIE_RXP_LN_IO PIE_RXN_LN_IO,0 PIE_TXP IO,0 PIE_TXN IO Z_SIN0_U_IO Z_LK_U_IO Z_SOUT_U_IO Z_SYN_U_IO, Z_RST#_U_IO,0 SMI IO OP_S#_IO US_PP_IO US_PN_IO,0 LK_PIE_US_PH_IO,0 LK_PIE_US#_PH_IO,0 PIE_RXP_US_IO,0 PIE_RXN_US_IO Z_MI_LK_IO Z_MI_T_IO _LN_M_R_IO US_M_R_IO PR Swap Pin, and, PR Swap Pin, to, FP_P_HOL SIE SIE 0 00PF0V XEMI J0 _IO _LN_M_IO R0 _LN_M_R_IO PF0V _IO N +.VSUS_P +V_US_IO _IO 0 US_M_IO R0 US_M_R_IO +V_U 0.0UFV +.VSUS_P N 0PF0V 0.0UFV _IO SUSTEK OMPUTER IN US Port nndy_wang 00P_IO ate: Monday, May, 00 Sheet of.

68 _LN_M_R PF0V _US0_M_R FP_P_HOL SIE SIE +VSUS EHISEL#_PH +VS +VS VSUS_ON 0,, US_PP US_PN LK_PIE_LN +VSUS LK_PIE_LN# PIE_TXN_LN PIE_TXP_LN PIE_RXP_LN PIE_RXN_LN PIE_TXP_ PIE_TXN_ Z_SIN0_U Z_LK_U Z_SOUT_U Z_SYN_U Z_RST#_U US_SMI# OP_S# 0 US_PP US_PN LK_PIE_US_PH LK_PIE_US#_PH PIE_RXP_US PIE_RXN_US MI_LK MI_T +VSUS_T +.VS PWR_LE- PIE_WKE#, UF_PLT_RST#,0,,,,0 PWR_SW# 0 0UF.V +VS 0 0.UFV PWR_LE- +VS 0 0 0UF.V 0UF.V +VSUS_T 0 0UF.V 0 0.UFV PJP0 MM_OPEN_MIL PJP0 MM_OPEN_MIL 0 0UF.V Q0 UMKN O_LI_E# Q0 UMKN O_PWR_LE_UP +VSUS +VS O_LI_E# 0, O_PWR_LE_UP 0, J0 SUSTeK OMPUTER IN TO ONN rieejesse ate: Monday, May, 00 Sheet of.0

69 EPX_GTE_SW# R0 N Ohm SW0 0 PF0V TP_SWITH_P N EPX_GTE_SW# R0 Ohm SW#_ON VX WIFI_SW# R0 Ohm SW0 N TP_SWITH_P 0 PF0V SW#_ON J0 SIE SW#_ON SIE WTO_ON_P PR MO MOS MER SUSTeK OMPUTER IN riesjesse ate: Monday, May, 00 Sheet of.0

70 PIEN_RXP0 PEX_TSTLK_OUT_N PIEN_RXN0 PIEG_TXP0 PIEG_RXP0 PEX_TSTLK_OUT +PEX_PLLV GPU_HOL_RST#_R PIEG_RXN0 PIEG_TXN0 PEX_TERMP_NV PEG_SLT_RST# PIEG_TXN0 PIEG_TXP0 GPU_PWR_EN# GPU_PWRON PEG_SLT_RST# PEREQ# GPU_PWROK NV_SENSE GPU_PWRON, +VSG +VPG +VSG +0.VSG +0.VSG +VPG +VSG +VS +VSG +VSG PIEG_RXP0 PIEG_RXN0 PIEN_RXN0 PIEN_RXP0 LK_PIE_PEG_PH LK_PIE_PEG#_PH GPU_HOL_RST#,0 UF_PLT_RST#,0,,,, GPU_PWROK,,0,, GPU_PRSNT# GPU_PWR_EN#,0 +0.VS_PWRG PEREQ# ate: Sheet of Monday, May, 00 SUSTeK OMPUTER IN.0 riesjesse 0 VG_nVII_NM-GE_PIE ate: Sheet of Monday, May, 00 SUSTeK OMPUTER IN.0 riesjesse 0 VG_nVII_NM-GE_PIE ate: Sheet of Monday, May, 00 SUSTeK OMPUTER IN.0 riesjesse 0 VG_nVII_NM-GE_PIE 0m 0m 0m ER 00.UF.V 00.UF.V 0 0.UF0V 0 0.UF0V R00 MOhm R00 MOhm 0.UF.V 0.UF.V G S Q0 N00 G S Q0 N00 T00 T00 PEX_LKREQ_N E PEX_TSTLK_OUT F0 PEX_TSTLK_OUT_N E0 PEX_RST_N PEX_REFLK 0 PEX_REFLK_N 0 PEX_TX0 0 PEX_TX0_N PEX_RX0 E PEX_RX0_N F PEX_TX PEX_TX_N PEX_RX G PEX_RX_N G PEX_TX PEX_TX_N PEX_RX F PEX_RX_N E PEX_TX PEX_TX_N PEX_RX E PEX_RX_N F PEX_TX PEX_TX_N PEX_RX G PEX_RX_N G PEX_TX PEX_TX_N PEX_RX F PEX_RX_N E PEX_TX PEX_TX_N PEX_RX E PEX_RX_N F PEX_TX PEX_TX_N PEX_RX G PEX_RX_N G PEX_TX PEX_TX_N PEX_RX F PEX_RX_N E PEX_TX PEX_TX_N 0 PEX_RX E PEX_RX_N F PEX_TX0 PEX_TX0_N 0 PEX_RX0 G PEX_RX0_N G PEX_TX PEX_TX_N PEX_RX F PEX_RX_N E PEX_TX PEX_TX_N PEX_RX E PEX_RX_N F PEX_TX PEX_TX_N PEX_RX G PEX_RX_N F PEX_TX PEX_TX_N PEX_RX G PEX_RX_N G PEX_TX E PEX_TX_N E PEX_RX F PEX_RX_N E PEX_IOV_ PEX_IOV_ PEX_IOV_ PEX_IOV_ E PEX_IOV_ F PEX_IOV_ G PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_0 E PEX_IOVQ_ F PEX_IOVQ_ G V_ J0 V_ J V_ J V_ J V_ L V_ M V_0 M V_ M V_ N V_0 N V_ N V_ N V_ N V_ N V_ N V_ N V_ N V_ P V_ P V_0 P V_ P V_ P V_ P V_ P V_ R V_ R V_ R V_ R V_ R V_0 R V_ R V_ R V_ T V_ T V_ T V_ U V_ U V_ W0 V_ W V_0 W V_ W V_ W V_ W V_SENSE_ W _SENSE_ W V_SENSE_ E _SENSE_ E V_ V_ V_ V_ V_ E V_ F PEX_SV_V G PEX_PLLV F PEX_TERMP G0 U00 NM-GE U00 NM-GE 0.UF.V 0.UF.V 0 0.0UFV 0 0.0UFV 00 TW 00 TW 00 0.UF0V c UF0V c00 0.UF.V 0.UF.V 00.UF.V 00.UF.V 00 0UF.V 00 0UF.V R0 00KOhm R0 00KOhm Q00 UMKN Q00 UMKN 0 0.UF0V 0 0.UF0V 00 0.UF0V c UF0V c00 0 UF.V 0 UF.V 0 0.UF0V 0 0.UF0V 0.UF.V 0.UF.V R00 0KOhm R00 0KOhm 00 NWS 00 NWS 0.UF.V 0.UF.V R00 0 % R00 0 % 0.UF.V 0.UF.V R00.KOhm % R00.KOhm % 00 0.UFV 00 0.UFV 0.UF.V 0.UF.V 00 0.UF0V c UF0V c00 00 NWS 00 NWS 0.UF.V 0.UF.V 0.UF.V 0.UF.V R0 0KOhm R0 0KOhm 0 0.UF0V c UF0V c00 L00 00NH L00 00NH 0 0.0UFV 0 0.0UFV 00 0.UF0V c UF0V c00 R00 0KOhm R00 0KOhm 00.UF.V 00.UF.V Q00 UMKN Q00 UMKN R00 0KOhm R00 0KOhm 00 UF.V 00 UF.V 0 0.UF0V c UF0V c00 00 UF.V 00 UF.V 0 UF.V 0 UF.V 0 0.0UFV 0 0.0UFV 0 0.UF0V c UF0V c UFV 0 0.0UFV 0 0.0UFV 0 0.0UFV 0 0.0UFV 0 0.0UFV R00 0KOhm R00 0KOhm 0 0.UF0V c UF0V c UFV 0 0.0UFV 00 0.UF0V 00 0.UF0V 0 0UF.V 0 0UF.V

71 F_0 F_ F_0 F_ F_QM +F_PLLV F_M F_QM0 F_QM F_QM F_ F_ F_ F_ F_M F_M F_ F_M F_M F_QM F_ F_M F_M F_0 F_ F_EUG F_ F_QS_WP F_ F_QS_WP F_ F_M F_ F_ F_ F_M F_ F_ F_L_TERM_ F_QM F_QS_RN0 F_M0 F_M F_ F_VREF F_ F_QS_WP F_ F_ F_ F_0 F_M F_ F_M F_ F_ F_ F_QS_WP F_ F_M0 F_M F_L_PU_ F_ F_ F_M F_M F_ F_ F_QS_WP F_M F_M F_QS_WP0 F_QS_RN F_ F_ F_ F_M F_ F_M0 F_ F_ F_QS_WP F_M F_ F_0 F_ F_ F_QS_WP F_ F_0 F_M F_QS_RN F_M F_M F_QS_RN F_ F_M F_ F_M F_QS_RN F_ F_ F_ F_M F_0 F_QS_RN F_L_P_VQ F_ F_ F_QM F_ F_QS_RN F_ F_ F_M F_ F_M0 F_ F_ F_M F_ F_QS_RN F_ F_QM F_ F_LK0# F_LK0 F_[..0] F_LK# F_QS_RN[..0] F_QS_WP[..0] F_M[0..0] F_QM[..0] F_LK +.VSG +.VSG +VPG +.VSG +.VSG ate: Sheet of ustom Monday, May, 00 SUSTeK OMPUTER IN.0 riesjesse VG_nVII_NM-GE_F ate: Sheet of ustom Monday, May, 00 SUSTeK OMPUTER IN.0 riesjesse VG_nVII_NM-GE_F ate: Sheet of ustom Monday, May, 00 SUSTeK OMPUTER IN.0 riesjesse VG_nVII_NM-GE_F 0mil. R0 KOhm % R0 KOhm % 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0 UF.V 0 UF.V 0.UF0V 0.UF0V 0.UF0V c00 0.UF0V c00 0.UF0V c00 0.UF0V c00 0.0UFV 0.0UFV L0 00Mhz l00 L0 00Mhz l00 R0 KOhm % R0 KOhm % 0.UF0V 0.UF0V R 0.Ohm % R 0.Ohm % R0 0KOhm R0 0KOhm 0 0.UF0V 0 0.UF0V 0 0.UF0V 0 0.UF0V.UF.V c00.uf.v c UF0V 0 0.UF0V R 0.Ohm % R 0.Ohm % UF.V UF.V F_0 F_ E F_ E F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ E F_ F F_ 0 F_ F0 F_0 F_ F F_ F_ E F_ F_ F_ F_ F_ F_ F_0 F_ F_ U F_ V F_ V F_ R F_ T F_ R F_ P F_ P F_0 F_ F_ F_ W F_ F_ W F_ W F_ V F_ F_ W F_0 W F_ W F_ F_ F_ F_ F_ V F_ R F_ V F_ V F_0 R F_ T F_ N F_ N F_QM0 F_QM F_QM F_QM F_QM T F_QM F_QM F_QM T F_QS_WP0 F_QS_WP F_QS_WP E F_QS_WP F_QS_WP T F_QS_WP F_QS_WP F_QS_WP T F_QS_RN0 F_QS_RN F_QS_RN E F_QS_RN F_QS_RN R F_QS_RN Y F_QS_RN F_QS_RN R F_VREF FVQ_0 FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ E FVQ_ F FVQ_ F FVQ_ F FVQ_0 F FVQ_ F FVQ_ F FVQ_ F FVQ_ H FVQ_ H FVQ_ J FVQ_ J FVQ_ J FVQ_ J FVQ_0 L FVQ_ L FVQ_ L FVQ_ M FVQ_ N FVQ_ U FVQ_ Y F_M0 F F_M J F_M F F_M M F_M N F_M M F_M K F_M J F_M J F_M G F_M0 G F_M J F_M M F_M K F_M G F_M L F_M K F_M K F_M G F_M K F_M0 H F_M M F_M H F_M F F_M J F_M G F_M G F_M M F_M K F_M J F_M0 L F_LK0 F F_LK0_N F F_LK N F_LK_N N _designs) M F_L_P_VQ F_L_PU_ F_L_TERM_ F_PLLV_ R F_LLV T F_PLLV_ F_EUG(S_for_GR U00 NM-GE F_EUG(S_for_GR U00 NM-GE 0 0.UF0V 0 0.UF0V 0.UF.V c00 0.UF.V c00 0.UF0V 0.UF0V 0 UF.V 0 UF.V R 0.Ohm % R 0.Ohm % 0.UF.V c00 0.UF.V c00

72 VG +VSG L0 00Mhz l00 GPU R0 0KOhm Optimus LVS.UF.V GPU UF.V GPU 0m (mil) 0.UF0V GPU.G page Unused VG _V tie to via a 0Kohm Other pins can be N. T0 0 0.UF0V GPU _VREF T0 +_V _RSET R0 Ohm % GPU G F E U00 _V _VREF _RSET NM-GE _HSYN _VSYN _RE _GREEN _LUE E E HSYN_GPU VSYN_GPU RE_GPU GREEN_GPU LUE_GPU RE_GPU R GPU % GREEN_GPU R GPU % LUE_GPU R GPU % +VSG ER U00J STRP0 STRP STRP0 STRP STRP STRP MULTISTRP_0 F MULTI_STRP_REF0_ MULTISTRP_ F0 MULTI_STRP_REF_ R0 0.KOHM % R0 0.KOHM % ER N N NV N_ N NV TESTMOE F N_ F _ R0 0KOhm NM-GE +VSG NM-PT EVIE I:0X0 +VSG R 0KOhm ROM_S_N Only Ext-ROM present then must PU ROM_S_N 0 G-0-00 Page 0 ROM_SI ROM_SI ROM_SO ROM_SO 0 ROM_SLK ROM_SLK VG_ROM_SL IH_SL VG_ROM_S IH_S +VSG UFRST_N N R 0KOhm TESTMOE_NV R 0KOhm +VPG L0 00Mhz l00 GPU R 0KOhm Optimus.UF.V GPU UF.V GPU T0 +IFP_PLLV IFP_RSET 0m R0 KOhm % GPU_ U00E IFP_PLLV IFP_RSET IFP_TX0_N IFP_TX0 IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX V V Y W V W LVS_L0N_GPU LVS_L0P_GPU LVS_LN_GPU LVS_LP_GPU LVS_LN_GPU LVS_LP_GPU R.KOhm R0.KOhm % R.KOhm R.KOhm R.KOhm R.KOhm STRP0 STRP STRP R KOhm R KOhm % R 0KOhm R KOhm R 0KOhm R.KOhm ROM_SO ROM_SI ROM_SLK VG_ROM_SL VG_ROM_S nvidia G-0-00_V0_secured.pdf section..kohm RN0.KOhm RN0 +VSG +.VSG L0 00Mhz l00 GPU R 0KOhm Optimus.UF.V GPU UF.V GPU 0.UF0V GPU +L_IOV 0.UF0V GPU 0m V V IFP_IOV IFP_IOV IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX W W LVS_LLKN_GPU LVS_LLKP_GPU PUN-0 setting 0 IFP_TX_N IFP_TX GPIO0 N GPIO0_NV T0.G page Unused IFP IFP_PLVIFP IOV tie to via a 0Kohm Other pins can be N. NM-GE HMI +VSG +IFP_PLLV L0 00Mhz l00.uf.v +IFP_IOV +VPG L0 00Mhz l00.uf.v 0 UF.V UF.V 0m IFP_RSET 0.UF0V m 0.UF0V R0 KOhm % U00F P IFP_PLLV R IFP_RSET IFP_UX_IW_S_N IFP_UX_IW_SL IFP_L_N IFP_L IFP_L_N IFP_L IFP_L_N IFP_L J IFP_IOV IFP_L0_N IFP_L0 GPIO G G J H K L M M N P G _T_NV R Ohm HMI_T_GPU _LK_NV R Ohm HMI_LK_GPU HMI_LKN HMI_LKN HMI_LKP HMI_LKP HMI_TXN0 HMI_TXN0 HMI_TXP0 HMI_TXP0 HMI_TXN HMI_TXN HMI_TXP HMI_TXP HMI_TXN HMI_TXN HMI_TXP HMI_TXP HMI_HP_VG NM-GE +VSG +IFP_PLLV IFP_RSET U00G N IFP_PLLV M IFP_RSET _T_NV _LK_NV.KOhm RN0.KOhm RN0 R0 KOhm % IFP_UX_IX_S_N IFP_UX_IX_SL +IFP_IOV IFP_L_N IFP_L IFP_L_N IFP_L H IFPE_IOV IFP_L_N IFP_L E IFP_L0_N IFP_L0 GPIO F F F R SUSTeK OMPUTER IN VG_nVII_NM-GE_isp riesjesse NM-GE 0KOhm Monday, May, 00 ate: Sheet of.0