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1 NANO COMMUNICATION 23 No.4 15 Effects of Annealing Process on RF poly-si TFTs with Various Channel Wire Widths : : Abstract The high-frequency performance of trigate polycrystalline silicon thin-film transistors (poly- Si TFTs) with different annealing methods, rapid thermal annealing (RTA) or low-temperature microwave annealing (MWA) are investigated. MWA exhibits sufficient dopant activation efficiency, suppressed punch-through characteristics and good short channel effect control of poly-si TFTs than does rapid thermal annealing. In addition, the variation of the cutoff frequency (f T ) and the maximum oscillation frequency (f max ) with the width of the channel wire (W 0 ) is also investigated. A poly-si TFT with a short channel and a narrow channel wire, annealed using microwave, has a high driving current, a good gate controllability, and a better highfrequency performance than that annealed by rapid thermal annealing. Keywords Microwave Annealing (MWA) Poly-Si TFTs Cutoff Frequency

3 16 (Liquid Crystal Display, LCD) (Low-Temperature Polysilicon, LTPS) (TFT- LCD) (a-si) (System On Panel, SOP) [1-5] : (Drain-induced Barrier Lowering, DIBL) (Short-channel Effects, SCE) (Fin

2 3 16 (Liquid Crystal Display, LCD) (Low-Temperature Polysilicon, LTPS) (TFT- LCD) (a-si) (System On Panel, SOP) [1-5] : (Drain-induced Barrier Lowering, DIBL) (Short-channel Effects, SCE) (Fin Field-effect Transistor, FinFET) (RF) 200 nm n cm kev W 300 TEOS (Al-Si-Cu) Agilent N5245A HP 4142B (S-Parameter) - (On- Wafer Measurement) (Deembedding) 1(a) (Multiple Fingers Structure) (RF TFT) 1(b) A-A (TEM) (h) 85 nm (W 0 ) 130 nm 1.8 m 3.8 m W W=(W 0 +2h) (N f ) 63 m 2 3 W 0 =130 nm 3.8 m (I D -V G ) 6 p 2 m 100 nm (E-beam) LPCVD 50 nm (TEOS) 1 (a) RF TFT ;(b) A-A TEM

3 奈米通訊 NANO COMMUNICATION 23卷 No. 4 退火機制對於不同通道線寬之射頻複晶矽薄膜電晶體之影響 17 圖2 W0=130 nm 在不同通道長度下使用不同退火機制的 ID-VG 圖 (a)vds=0.1 V;(b)Vds=2 V 圖3 圖4 磷濃度在劑量為 5E15 ions/cm2 的 SIMS 分佈圖圖5 W0=130 nm 和 3.8μm 於通道長度 1μm 使用不同退火機 W0=3.8 μm 在不同通道長度下使用不同退火機制的 ID-VG 圖 (a)vds=0.1 V;(b)Vds=2 V 圖單一通道寬度W0=3.8μm元件當通道長度小於700 nm 使用傳統快速熱退火時可觀察到大關閉電流和穿透效應(Punch-through) 然而不論單一通道寬度大小 W0=130 nm與3.8μm 當VDS=0.1 V且使用微波退火的狀態制的 ID-VG 圖下通道長度即使微縮到200 nm 還能擁有很優異的開關特性 ION/IOFF值分別為8 106 A/A和6 107 A/A 圖4為 31 高頻特性 P濃度的二次離子質譜儀分析圖(SIMS) 使用快速熱退火1000 1秒的摻雜分佈在尾端與峰值區域有明顯的擴圖6和7為單一通道線寬W 0=130 nm 1.8μm與3.8 散然而使用微波退火的摻雜分佈則和as-implanted 的 μm的元件在不同汲極電流下之截止頻率與最大震盪頻摻雜分佈較為相似這些結果顯示低溫微波退火可以有率從圖中可觀察到使用快速熱退火或微波退火的元件效抑制源極與汲極摻雜的擴散此外指狀閘極結構也其截止頻率(fT)與最大震盪頻率(fmax)都會隨著W0增加而上可以改善閘極的控制力圖5為W0=130 nm與3.8μm的元升大線寬(W 0=1.8 μm和3.8μm)元件在採用快速熱退件在通道長度為1μm的情況下使用不同退火機制的轉火時會得到比微波退火更高的截止頻率與最大震盪頻換特性曲線圖由於微波退火有較少的摻雜擴散且較率如圖8 然而小線寬元件(130 nm)在使用快速熱退短W0可提高閘極控制能力故當W0=130 nm時使用微火時其最大震盪頻率則會比使用微波退火技術的元件波退火的元件有最小的汲極引致能障下降(DIBL)值汲極來的小然兩者確有相似的截止頻率為了分析不同單引致能障下降在此處的定義為 VGS/ IDS=10 A 一通道寬度W0與退火機制對高頻特性的影響此處我們 -8 使用小訊號模型來萃取不同結構之寄生電阻電容轉導等參數本文萃取S參數的等效電路模型為Lovelace

4 W 0 RF TFT 8 W 0 W 0 7 W 0 RF TFT 9 [6] 9 (f T ) : (1) g m C gs C gd - - (W 0 = m) 10 (W 0 =1.8 m 3.8 m) 11 W 0 (Fringing Capacitance) [7] W 0 (W 0 =1.8 m 3.8 m) (Overlap Capacitances) (W 0 =1.8 m 3.8 m) (W 0 =130 nm) (Poly-depletion Effect)

5 奈米通訊 NANO COMMUNICATION 23卷 No. 4 退火機制對於不同通道線寬之射頻複晶矽薄膜電晶體之影響 19 的串聯電阻與汲源極電阻(R ds =1/g ds ) 使用微波退火的元件相較於使用快速熱退火的元件具有較低的串聯電阻值其主要原因為微波退火有較少的摻雜外擴散(Outdiffusion)[10] 如圖12 而使用快速熱退火的元件相較於使用微波退火的元件則有較低的汲源極電阻值這是由於快速熱退火有較大的摻雜擴散與較短的通道長度首先我們分析不同退火方式對大尺寸(W 0 =1.8μm和 3.8μm)元件之最大震盪頻率的影響雖然使用微波退火圖 10 的元件相較於使用快速熱退火的元件有較高的汲源極電不同熱退火條件之 RF TFT 的轉導值阻值與較低的串聯電阻值然而使用微波退火的元件其最大震盪頻率依然低於使用快速熱退火的元件由此圖 11 不同熱退火條件之 RF TFT 寄生電容值 (a) Cgs 值 (b) Cgd 值圖 12 不同退火機制之 RF TFT 寄生電阻 Rg 與 Rd 圖 13 不同退火機制之 RF TFT 的 Rds 值閘極反轉層電容和驅動電流下降轉導值也連帶受到影響當閘極的長度與寬度微縮時會使複晶矽空乏效應越亦嚴重這主要是受到角落與邊緣的空乏效應(Corner and Edge Depletion)所影響 [8] 當單一通道寬度W 0=130 nm時複晶矽空乏效應佔主導地位如圖8之插圖故可觀察到使用快速熱退火的元件其轉導值會隨著W0減少而下降而使用微波退火的元件其轉導值則會隨著W0減少而增加這要歸功於三閘極結構優異的閘極控制力由於轉導值和閘極電容相互抵銷因此使用快速熱退火和使用微波退火的元件有相似的截止頻率值最大震盪頻率(fmax)的近似公式為[9]: (2) 其中g ds為輸出轉導 R g和r d分別代表閘極和汲極的串聯可知使用微波退火的大尺寸(W0=1.8μm和3.8μm)元件有電阻圖12和13分別為使用快速熱退火與微波退火元件較低的最大震盪頻率乃是由於截止頻率較低所至接著我們分析小尺寸(W0=130 nm)元件於不同退火機制下最大

3 20 1 L=1 m W 0 =130 nm (I ON /I OFF ) V DS =0.1 V : V GS = 5 V V DS = 2 V 200 nm (W 0 =130 nm) Punchthrough (>10 7 A/A) (W 0 =130 nm) Punch-through L=200 nm 1.2 GHz 2.

6 L=1 m W 0 =130 nm (I ON /I OFF ) V DS =0.1 V : V GS = 5 V V DS = 2 V 200 nm (W 0 =130 nm) Punchthrough (>10 7 A/A) (W 0 =130 nm) Punch-through L=200 nm 1.2 GHz 2.17 GHz ( ) 1 L=1 m W 0 =130 nm [1] K. M. Lim et al. A High Resolution Poly-Si TFT LCD ] 9 [ Employing Analog Sample and Hold Driver, Displays - Technology and Applications, vol. 29, no5, pp. 497, [2] S. H. Chen et al. Design of Digital Time-Modulation Pixel Memory Circuit on Glass Substrate for Low Power Application, SID Digest, pp.1281, [3] K. S. Nah et al. A 16.7M Color VGA Display Driver IC with Partial Graphic RAM and 500Mb/s/ch Serial Interface for Mobile a-si TFT-LCDs, Solid-State Circuits Conference, ISSCC Digest of Technical Papers. IEEE International, pp.140, (W 0 ) [4] V. Tolis et al. LCD-related Technologies Next Generation of Poly-Si TFT Technology: Material Improvements and Novel Device Architectures for System-On-Panel (SOP), Sharp Technical Journal, no.92, pp.29-34, [5] Y. H. Yu et al. Ring-Based Direct Injection-Locked

7 NANO COMMUNICATION 23 No Frequency Divider in Display Technology, IEEE Microw. Wireless Compon. Lett., vol. 18, no. 1, pp. 752, Nov [6] D. Lovelace, Lovelace, J. Costa, and N. Camilleri, Extracting small-signal Model Parameters of Silicon MOSFET Transistors, in Proc. IEEE MTT-S Int. Microw. Symp., pp , May [7] W. Wu and M. Chan, Analysis of Geometry-dependent Parasitics in Multifin Double-gate FinFETs, IEEE Trans. Electron Devices, vol. 54, no. 4, pp , Apr [8] C. H. Choi, P. R. Chidambaram, R. Khamankar, C. F. Machala, Z. Yu, and R. W. Dutton, Dopant Profile and Gate Geometric Effects on Polysilicon Gate Depletion in Scaled MOS, IEEE Trans. Electron Devices, vol. 49, no. 7, pp , Jul [9] T. C. Lim and G. A. Armstronga, The Impact of the Intrinsic and Extrinsic Resistances of Double Gate SOI on RF Performance, Solid-State Electron. vol. 50, pp , [10]Y. J. Lee, T. C. Cho, S. S. Chuang, F. K. Hsueh, Y. L. Lu, P. J. Sung, H. C. Chen, M. I. Current, T. Y. Tseng, T. S. Chao, C. Hu, and F. L. Yang, Low-Temperature Microwave Annealing Processes for Future IC Fabrication-A Review, IEEE Trans. Electron Devices, vol. 61, no. 3, pp , Mar

NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94

NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz 23 90 CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94/188GHz LC class-b 0.70 0.75 mm 2 pad 1 V 19.6 ma (ƒ