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1 奈錄奈 1-1 CMOS 奈 1-2 邏路. 奈金 , 奈奈奈料 4-3 奈料 4-4 奈奈 5-3 奈量錄 I 1

2 奈 1-1 CMOS 奈了數度都不都 innovation 參數 1 奈更 1. 諸 (after ITRS roadmap 2003) 神數 2E10 神連數 100~10,000 量 1.3 kg 600cm 3 率 W 1E12 bits 料理度 1E10 bits/sec CMOS (complementary metal oxide silicon) 利 scaling 來來度 constant electrical field scaling 率 power density technology node IC 連度 MOSFET 度更 MOSFET 度 26mV V T constant electrical field scaling 0.2V off-state 流 2 流 I Dsat V DD constant electrical field 來 1-1 率度 1.3 率 standby power 3 率若 SiO 2 數更漏流率率 bipolar transistor 90 年 CMOS 路 CMOS 路率 IC 量 1-3 率來奈 2

3 V/α t ox /α GATE WIRING W/α n - n + source drain L/α x d /α psubstrate, doping α*n A Voltage: V/α Oxide: t ox /α Wire width: L/α Gate Width: x d /α Substrate: α*n A RESULTS: Higher Density: ~ α classic scaling T ox (Å) V dd ( ) V t ( ) Higher Speed: ~α 0.1 Power/ckt: ~1/α Power Density: ~ Constant Gate Length, Lgate(µm) 1-1. MOS SiO 2 度 V dd V t 度 [1], after B. S. Meyerson, 2004 度 T ox Å Leff and Vdd Active Power Density ~ 1.3X/generation Passive Power Density ~ 3X/generation Gate Leakage Power Density > 4X/generation Power (W/cm 2 ) 1E+03 1E+02 1E+01 1E+00 1E-01 1E-02 1E-03 1E-04 Standby Power Density Active Power Density 1E Gate Length (µm) 率度 [1]. after B. S. Meyerson, 2004 率路 HP high performance LOP low operation power LSTP low standby power HP 度 Pentium CPU 率不 LOP 率 note book IC 若量 standby power 3

4 不 LSTP 不率量不省 Result : CMOS power densities escalate unacceptably Bipolar Module Heat (watts/cm 2 ) CMOS 5W/cm bipolar CMOS 路率 [1], after B. S. Meyerson 2004 CMOS 率流漏 high k dielectrics 來 oxynitride C g ε = 數 ε t 度 1-4 度 < 2nm 0.25nm 2V 漏流 10X 度 3nm 漏流 1E-4 A/cm 漏流度度 [2] 1997 IEEE 4

5 了漏 HP 流 V t 0.2V 了率 maximum osilation frequency f max 金 metal gate 來 poly gate 降數 CMOS high k metal gate CMOS 率更 CMOS 列列利 strain 率 mobility 利 silicon on insulato SOI 數流 current drive memory 邏 logic 列列 2 列了路 architecture 列 1 列 Emerging Research Devices Emerging Technology Sequence Emerging Technology Vectors 列 Cellular array Defect tolerant Biologically inspired Quantum computing Architecture 列 RSFQ Floating body DRAM Nano FG SET Insulator resistance change Molecular Logic 列 Phase change 1-D structures Resonant tunneling SET Molecular QCA Spin transistor Memory 列 Transport enhanced FETs UTB single gate FET Sourec/Drain engineered FET UTB multiple gate FET Quasi ballistic FET Nonclassical CMOS Figure 38 Emerging Technology Sequence Risk 1-5. ITRS 2003 [3], after ITRS roadmap

6 1-2 邏 MOS 易 IC strained Si Intel prescott pentium chip 例 NMOS tensile stress 力 PMOS 力 compressive stress 洞率 mobility µ 流 W I D ~ µ ( V ) α CV Cox GS Vt 度 t = HP 路 L I D strained Si SOI SSOI 1-6. SOI (after ITRS roadmap 2003) ultra thin body SOI 若 Si 度 4nm 度 nm 22nm buried oxide BOX 列 1-6 欄 SOI Si doping 度 1-7 mobility 若 Si 度 Si BOX 度 mobility 降 6

7 Electron Mobility, µ eff (cm 2 /Vs) Universal Mobility Vertical E-field, E eff (MV/cm) Hole Mobility, µ eff (cm 2 /Vs) Universal Mobility Vertical E-field, E eff (MV/cm) 1-7. 洞率 1-8. / FET(after ITRS roadmap 2003) 7

8 1 MOS 流 10 利 Schottky 降 I on on state 流 1-8 I off 不流 / 降 / / 1-8 浪了 channel 1-9 若 4 gate 4 流 4 oxide 流 1-9. MOSFET 若度 electro static 流 scaling MOS N-gate N 2 若 Si gate control 更 Tied gate 連 (after ITRS roadmap 2003) 8

9 Independently switched gates, planar conduction LOP and LSTP CMOS Vertical conduction HP, LOP, and LSTP CMOS 立 (after ITRS roadmap 2003) FET 離若連 tied double gate FET 若不 independent switch gate 流行 1-11 行度度 sidewall conduction 1-10 度行 planar conduction 1-10 ITRS international technology roadmap of semiconductor CMOS SOI high k metal gate 16nm MOS 度 7nm 度 7nm 2019 年 CMOS 度 2 MOSFET 邏 1. Rapid Single Flux Quantum RSFQ Josephson 量量量 1 flux quanta 0 flux 0 1 狀量 0.3µm 度 250GHz 度度 77K 利 High Tc super conductor HTS 度 2. 1D carbon nanotube Si wire 1D 1D bulk 9

10 2. 邏 (after ITRS roadmap 2003) Availability Sequence Device FET RSFQ [A,B,C] 1D structures Resonant Tunneling Devices Types Si CMOS JJ CNT FET RTD-FET Supported Architectures Cell Size (spatial pitch) Density (devices/cm 2 ) NW FET NW heterostructures Crossbar nanostructure Conventional Pulse Conventional Cross-bar RTT Conventional CNN SET CNN SET Molecular QCA (E) Spin transistor 2-terminal 3-terminal FET 3-terminal bipolar transistor NEMS Molecular QCA Memorybased QCA E:QCA M:QCA QCA Spin FET (SFET) Spin-valve transistor (SVT) Quantum Programmable logic 100 nm 0.3 µm 100 nm 100 nm 40 nm Not known 60 nm 100 nm 3E9 1E6 3E9 3E9 6E10 1E12 3E10 3E9 Switch Speed 700 GHz 1.2 THz Not known 1 THz 1 GHz Not Known 30 MHz 700 GHz Circuit Speed Switching Energy, J Binary 30 GHz GHz 30 GHz 30 GHz 1 GHz Nb [> ] < 1 MHz (NEMS) > [> ] [C] (NEMS) 1 MHz 30 GHz [E:> ] [E] M:> Throughput GBit/ns/cm N/A Gain Must be>>1 for all devices, See Table 63b for experimental values Operational Temperature RT 4K(Nb) 77K(HTS) 20K(M g B 2 ) RT RT 20 K RT E:QCA Cryogenic M:QCART CD Tolerance Critical Not critical Not critical Very critical Very critical Not critical Very critical <2%(M:QCA) Materials System Si Nb HTS Mart Complex Circuit Demonstrated CNT Si - - Si-Ge See Table 63b - Si C-60 Al/Al 2 O 3 (E: QCA) Cryogenic (SFET) RT (SVT) Critical - (SFET) Si/FM(SVT) 料 1 率 2 數 coherent 10

11 3. Resonant tunneling 流 - 流 barrier 度數數不易度 1THz 4. single electron transistor SET MOSFET / 來 pn 量度量若 2 nm 度 20K 度 1GHz 度 cm -2 流數路 fan out 不率 5. molecule 利連利 overlap 流降流利例金 filament 益 6. Quantum cellular automata QCA 利 local interconnect 流力不列不流利力 E QCA 力 M QCA 例利 4 量 4 落 1-12 狀 AD BC 量量離量 20nm 60nm 利邏路 QCA 更 celluar non-linear network CNN inverter 7 QCA QCA 度利 THz MHz 度 7K A B C D 量 7. 利 spin-fet spin-valve spin-fet 利 FET ferromagnetic 料 spin-polarized spinvalve 11

12 BJT 都 ferromagnetic nonmagnetic 料 gain spinfet 3. (after ITRS roadmap 2003) Present Day Baseline Technologies Phase Change Memory Floating Body DRAM Nano-floating Gate Memory Single/Few Electron Memories Insulator Resistance Change Memory Molecular Memories Storage Mechanism Engineered Device Bi-stable DRAM NOR Flash OUM ITDRAM Tunnel barrier SET MIM Types switch Or nanocrystal Availability ~2006 ~2006 >2006 >2007 ~2010 >2010 Cell Elements 1T1C 1T 1T1R 1T 1T 1T 1T1R 1T1R Initial F 90 nm 90 nm 100 nm 70 nm 80 nm 65 nm 65 nm 45 nm Cell Size 8F F 2 ~6F 2 ~4F 2[A] ~6F 2 ~6F 2 ~6F µm µm µm µm µm µm µm 2 Not known Access Time < 15 ns ~ 80 ns <100 ns <10 ns [A,C] <10 ns <10 ns Slow ~10 ns Store Time < 15 ns ~ 1 ms <100 ns <10 ns [A,C] <10 ns <100 ns <100 ns ~10 ns Retention Time 64 ms yrs >10 yrs <10 ms [A] >10 yrs ~100 sec ~1 year ~1 month E/W Cycles Infinite 1E5 >1E13 >1E15 [A] >1E6 >1E9 >1E3 >1E15 General Advantages Challenges Density Economy Non-volatile Multi-bit cell Non-volatile Low power Rad hard Multi-bit cells Density Economy Non-volatile Density Fast read and Low power write Multi-bit cells Scaling Scaling Large E/W Need SOI Material quality current Retention versus New scaling Materials Dopant and integration fluctuation Endurance Low voltage Multi-bit cells Density Low power 3D potential Defect tolerant Dimension New Volatile control for RT operation materials and Thermal stability integration Slow access Background Speed versus charge R trade-off disturb Maturity Production Production Development Demonstrated Research Research Research Research Research Activity

13 1-3 利 CMOS platform 例 4 FET SRAM static random access memory 1 1 1T1C DRAM 3 行 cell element DRAM dynamic Random access memory Flash 列 1 2 欄 1. PCM phase change memory OUM ovonic unified memory 利流 chalcogenide vs 不 cell elements ITIR 利 SOI partially depleted MOSFET floating body floating body DRAM cell 3. floating gate MOSFET nanofloating gate memory NFGM 1 / 洞 2 gate 奈 4. 利量 1 數來 conductance 量 5. Insulator Resistance change Memory 利金 - - 金 MIM 見 SrZrO 3 Ba Sr TiO 3 MIM 不讀不不狀 RC 度 6. 利連不度不識來 1-4 路奈 MOSFET 不 MOSFET 路路不奈路 1. Parallel cellular Array 行列 1 QCA 利來 2 CNN Cellular Nonlinear Network 數來狀數連數利狀數數 VLSI 易 2. Defect tolerant architecture 奈度利 redundant 奈路不良路 3. bio inspired architecture 利類路 13

14 類利量連連行理奈 4. 量 (coherent quantum computing), 量利數理 qubit qubit 利 qubit 利數行行度讀料數讀數 14

15 參 1. B. Meyerson IBM Innovation the future si technology 90nm and beyond Taipei Taiwan Jan Y. Taur IEEE spectrum July Semiconductor Industry Association. The International Technology Roadmap for Semiconductors, 2003 edition. International SEMATECH:Austin, TX,

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