The World of MEMS

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1 先進電子封裝設計導論 (Introduction to IC Packaging) 饒達仁助理教授 (Da-Jeng Jeffrey Yao) 國立清華大學奈米工程與微系統研究所 1

2 Outline Traditional IC Packaging Packaging Design First level of Packaging Wafer Bonding Chip (Die) Bonding and interconnection Chip to Module Technology Enclose and Encapsulation Second level of Packaging PCB Technology Reliability Future Trend 2

3 積體電路的製作流程 3

4 Why Worry About Packaging? The package is integral to the final product You don t have a product until its in a package Package is 40-60% of product cost Costumed packaging solutions have long lead time Packaging design must be a part of product design, not an afterthough Consider product trade-offs upfront 4

5 Traditional IC Packaging 5

An Overview of Packaging Process Wafer level functional test Separate into individual die (chip) Mechanically attach to package or chip carrier (die bonding)

6 An Overview of Packaging Process Wafer level functional test Separate into individual die (chip) Mechanically attach to package or chip carrier (die bonding) Single chip module or multichip module Electrically attach to package (wire bonding) Enclose, encapsulate, seal package Functional test at package level Sell 6

7 Typical Electronic Packaging Hierarchy Zero Level : Transistor within IC First Level : Chip to module (chip carrier) Second Level: Module to PCB (card) Third Level: PCB to mother board Source: Low cost flip-chip technologies, John Lau,

8 Ref: Microelectronic Packaging, M.Datta etc. pp. 16, CRC Press,2004 8

9 Chip-Packaging Interconnection Ref: Microelectronic Packaging, M.Datta etc. pp , CRC Press,2004 9

10 IC Package Families 金屬罐式構裝單列式構裝交叉引腳式構裝雙列式構裝小型化構裝四邊平面構裝針格式構裝無引腳晶料承載器引腳晶料承載器 Package Family Characteristic Example In-line Small outline Quad surface mount Leads on one or opposing package side Leads on two or four sides, small body Leads on four sides, large body SIP, PDIP, CERDIP SOJ, SOP, TSOP PLCC, PQFP, LDCC Grid array Pins or pads placed in an Pin or pad grid array on body array, BGA Also find from 10

11 Ref: 微系統封裝原理與技術, 邱碧秀著, 滄海書局,

12 Ref: 微系統封裝原理與技術 12, 邱碧秀著, 滄海書局, 2005

13 Glossary of Acronyms BGA: Ball grid array CERDIP: Ceramic dual in-line package CERQUAD: Ceramic quad flatpack CLCC: Ceramic leadless chip carrier CPGA: Ceramic pin grid array C4: Controlled collapse chip connection EQFP: Enhanced plastic quad flatpack FQFP: Fine pitch quad flatpack GQFP: Guard ring quad flatpack ILB: Inner lead bonding LDCC: Leaded ceramic chip carrier LGA: Land grid array MCR: Molded carrier ring MQFP: Metric quad flatpack MQUAD: Metal quad flatpack OLB: Outer lead bonding PCB: Printed circuit board PDIP: Plastic dual in-line package PGA: Pin grid array PLCC: Plastic leaded chip carrier PQFP: Plastic quad flatpack PWB: Printed wiring board QFP: Quad flatpack SBA: Solder ball array SIP: Single in-line package SOIC: Small outline integrated circuit SOJ: Small outline J-bend SOP: Small outline gull wing TAB: Tape automated bonding TCP: Tape carrier package TQFP: Thin quad flatpack TSOP: Thin small outline package VFQFP: Very fine pitch quad flatpack ZIP: Zig-zag in-line package 13

14 Packaging Design 14

15 IC Packaging Design Electrical design Thermal management Mechanical design 15

Heat dissipation problem Protection from environment Life time and reliability

16 Microelectronic (IC) Packaging Mechanical support by silicon substrate Electric connection Without wiring, IC is useless Power distribution (layout) Thermal management Heat dissipation problem Protection from environment Life time and reliability Variability of packaging styles DIP, TAB, BGA, flip-chip, etc Cost, performance, and size trade-offs 16

17 Packaging in Electrical Design Electrical problems relate to both Signal propagation between the devices Power distribution required to operate these devices 17

18 Delay Caused by Package Circuit density Input/Output (connections/cm 2 ) Interconnection length Wire material ability (line/cm) Propagation medium Example: IBM 3090 CPU ~ 17.2 nsec (>50% by package delay) 18

19 Microsystem with Interference and Noise Interference (controllable) Noise (random) Capacitive coupling: via stray capacitance C between the system and an external voltage Magnetic coupling: via mutual inductance M between the system and an external current Radiative coupling: from electromagnetic radiation impinging on the system Ground-loop coupling: from currents flowing between different ground points 19

20 Interference Problem Power-line interference: Resistive interference 20

21 Thermal Management 封裝體表面溫度 T P Heat Conduction q cond ( Tp Ts ) = λ b Heat Convection q conv = h( T T ) p Heat Radiation q radi a 4 = εσ ( T a T p 4 ) 21

22 Cooling Design for Products Ref: 微系統封裝原理與技術, 邱碧秀著, 滄海書局,

23 Mechanical Design: Ex: Stress Mismatch 23

for cooling L( αb αc )( T min T0 ) The difference in the displacement at heating and cooling is

24 Thermomechanical Deformation in Solder Joints The expansion difference between board and carrier for hearing L( αb αc )( T max T0 ) The expansion difference between board and carrier for cooling L( αb αc )( T min T0 ) The difference in the displacement at heating and cooling is given by Δ = L( αb αc )( T max Tmin ) The shear strain will be Δ L γ = = ( αb αc )( T max Tmin ) h h 24

25 Multidisciplinary Issues In Package Design Decisions Factors Considerations Leadcount (no. of pins) Chip requirements Electrical requirements, cost, size Physical layout Electrical needs Size, power distribution Form (type) factor Package material Construction and layup Pin though-hole (PTH) or surface mount technology (SMT) Chip protection requirements Thermal requirements Supplier capability PCB assembly capability Mechanical requirements (reliability), sealing, cost Cost, compatibility with other materials Reliability requirements Chip assembly capability 25

26 Manufacturing (Wafer Wafer and Chip Bonding) 26

27 Bonding Techniques on Each Level Ref: 微系統封裝原理與技術, 邱碧秀著, 滄海書局,

28 Classifying Wafer Bonding Direct wafer bonding No intermediate layer Indirect wafer bonding An intermediate layer or adhesive Heat-assisted bonding Fusion, Eutectic Electrical field associated bonding Anodic Chemistry-assisted bonding Adhesive 28

29 Fusion Wafer Bonding For 200mm wafer with 0.35um process and above, the spec for curvature is < 50um. 29

30 Anodic Bonding 30

31 Eutectic Bonding 31

32 Application of Eutectic Bonding (Au-Si Eutectic Bonding) 32

33 Example of Au-Si Eutectic Bonding (a) Chip (Si) Substrate Gold film (b) Chip (Si) Substrate Gold film (c) Chip (Si) Substrate Preform eutectic Au/Si Procedure: Deposit 150Å Cr/1500 Å Pt/1500~5000Å Au film on substrate. Heat up to C in N2 ambient. 33

34 Wafer Bonding Comparison Various methods with a range of characteristics Anodic and direct bonding may need internal getter to get low vacuum levels in cavity 34

35 Wafer Bonding Systems 35

36 Manufacturing (Chip Bonding and Interconnection) 36

37 First Level Package Wafer -> Chip -> Die Attachment on a package -> Wire bonding -> Encapsulation 37

38 Ref: 微系統封裝原理與技術, 邱碧秀著, 滄海書局,

39 Al or Au Wedge Wire Bonding Al wedge to Al pad, Au wedge to Au pad Room temperature, pressure, and ultrasound Metal intermixing results in solid joint Ultrasound helps disrupts oxide films, enhances interdiffusion Al-to-Au bond at package can cause purple plague (AuAl 2 ) 39

40 40

41 Tape Automated Bonding (TAB/TCP) Procedure From Prof. Chih Chen 41

42 From Prof. Chih Chen 42

Flip-Chip Bonding Reduced signal inductance/ capacitance This is a key factor in high speed communication and switching devices Reduced power/ground inductance Power can be brought directly into the

43 Flip-Chip Bonding Reduced signal inductance/ capacitance This is a key factor in high speed communication and switching devices Reduced power/ground inductance Power can be brought directly into the core of the die, rather than having to be routed to the edges. This greatly decreases the noise of the core power, improving performance of the silicon Higher signal density/die shrink The entire surface of the die can be used for interconnect, rather than just the edges. Because flip chip can connect over the surface of the die, it can support vastly larger numbers of interconnects on the same die size 43

44 44

45 Chip to Module Technology 45

46 Traditional Single Chip Module Packaging Ref: 微系統封裝原理與技術, 邱碧秀著, 滄海書局,

47 Module Assembly Schemes Multichip Module (MCM) 47

48 Single-Chip VS Multichip Module Packaging For high density packaging Less lead requirements, but more interconnections Smaller size but complicated design (layout) 48

Function of Multichip Package Remove heat effectively from the chips Provide interconnections between all the chip with as many circuits as high a circuit performance as available to the multichip

49 Function of Multichip Package Remove heat effectively from the chips Provide interconnections between all the chip with as many circuits as high a circuit performance as available to the multichip substrate Provide wiring density with high-conductivity metal to interconnect all the chips with minimum chip-to-chip spacing Provide multichip substrate connections for signal and power distributions Provide protection to all the chip and the multichip substrate itself 49

50 Packaging Efficiency of Various Packages P eff = Total Total active silicon area active multichip packaging area 50

51 Chip Stacked Packaging (CSP) 51

52 52

53 CSP VS Stacked MCM 53

54 3D Packaging Ref: 微系統封裝原理與技術, 邱碧秀著, 滄海書局,

55 Enclose and Encapsulation 55

Seal and Encapsulation Packaging sealing and encapsulation are for chip protection Condensed moisture on a device's surface during operation has been shown to lead to the

56 Seal and Encapsulation Packaging sealing and encapsulation are for chip protection Condensed moisture on a device's surface during operation has been shown to lead to the principle causes of failure in the field One packaging method designed to prevent performance degradation due to moisture's deleterious effects is the hermetic package 56

57 Ways for Encapsulation Liquid Encapsulation Printing Encapsulation 57

58 PCB Technology (Second Level Packaging) 58

59 59 Ref: Microelectronic Packaging, M.Datta etc. pp. 16, CRC Press,2004

60 印刷電路板在電子產業中的定位 Ref: 印刷電路板概論 - 養成篇, 台灣電板產業學院, 全華科技 2005.

61 基板材料之應用

62 印刷電路板結構分類 Ref: 印刷電路板概論 - 養成篇, 台灣電板產業學院, 全華科技

PCB Interconnection 1950-1960 間, 主要是蝕刻銅的技術製造, 使其在單面形成金屬線路, 接著在安裝電子零件時, 用焊接固定或連接

63 PCB Interconnection 間, 主要是蝕刻銅的技術製造, 使其在單面形成金屬線路, 接著在安裝電子零件時, 用焊接固定或連接由於零件縮小化, 需要在一片 PC 板上, 裝載更多的零件, 雙面線路配的方法即產生 ( 如圖 ) Ref: 印刷電路板概論 - 養成篇, 台灣電板產業學院, 全華科技 2005.

64 線路製作流程 Ref: 印刷電路板概論 - 養成篇, 台灣電板產業學院, 全華科技 2005.

65 多層 PCB VIA ( 用以提高接線密度 ) HOLE Ref: 印刷電路板概論 - 養成篇, 台灣電板產業學院, 全華科技 2005.

66 Reliability 66

67 IC Package Reliability Problems in packaging affect your bottom line! IC world has 40 years on the learning curve 67

68 Reliability 圖 5.3 黏晶膠內吸收的水份加熱後蒸發成水蒸氣而在黏晶膠內形成孔洞. (a) 吸收的水份少, 孔洞小 ; (b) 吸收的水份多, 孔洞大, 造成爆米花現象, 而產生剝離. 68

69 Failure Mechanisms and Design for Reliability 69

70 How to Solve the Reliability Problem? 70

71 Qualifying Packages How do you know your package is OK? US Military standard 883: how to test microelectronics As a publicly available standard, specific testing methods are supported by test equipments Also used in industry Failure mechanism well understood US Military spec. available on-line default.asp Search for MIL-STD Mbytes (685 pages) 71

72 Die Attach Strength Die shear strength (2019.5) Die shears Die separates from DA Die and die attach separate from package Failures: min shear strength (1.0X) Die separation <1.25X min strength + <50% adhesion Die separation <2X min strength + <10% adhesion Die >80 mil must withstand >2.5 kg or multiple as above 72

73 Pull Test Used to Test Bond Integrity 73

Is a Sealed Package Hermetic? Package leak rate MIL-STD 883 1014.9: leak rate < 5E-8 atm cm 3 /s for small packages 0.

74 Is a Sealed Package Hermetic? Package leak rate MIL-STD : leak rate < 5E-8 atm cm 3 /s for small packages 0.1 cm 3 takes about 3 weeks to exchange gas Vacuum sealed package? Package moisture content MIL-STD Moisture < 5000 ppm Need low leak rate! Hard to qualify packages for 20+ year lifetime! 74

75 Future Trend 75

76 IC 產品特性驅動封裝技術之演進及變革 Ref: 微系統封裝原理與技術, 邱碧秀著, 滄海書局,

77 Evolution of Package Type 77

78 Future Trend Flip-Chip plus CSP MCM & PCB solder bonding 78

79 Thank You! 饒達仁教授 ( 清華大學奈米工程與微系統研究所 ) 工程一館 510 室 (03) ~42850 djyao@mx.nthu.edu.tw 79

P.1

P.1 P.1 P.2 1. 2. IC 3. 4. IC 5. P.3 (Interconnection).. P.4 (Wafer) (Chip) (MCM) P.5 電子構裝之主要功能電源供應層 1.有效供應電源信號分佈層 2.提供信號傳輸協助散熱保護元件 3.協助排除耗熱 4.保護電子組件 5.建構人機介面 Images 3D Graphics 建構人機介面 P.6 DIP Dual In-Line